Signal Descriptions

AD CAMAC Link
- PIOX
- PIOR
- BTR
RD CAMAC Link
- XD
- RD
MDAT
TCLK and BSCLK

AD CAMAC Link

The AD CAMAC link is a 10MHz modified manchester signal. A signal transition always occurs at the beginning of the 100 nanosecond bit cell. A transition within the cell indicates a "1" and no transition indicates a "0".

AD CAMAC PIOX

PIOX Frame 1

H1 H2 15.......................08 07........00 T1 T2
0 0 CRATE ADDRESS P 1
H2 being 0 indicates a 16 bit data frame.

PIOX Frame 1
H1	H2	15.......................08	07........00	T1	T2
0	0	CRATE ADDRESS		P	1
H2 being 0 indicates a 16 bit data frame.

PIOX Frame 2

H1 H2 15...............................11 10 09....................06 05 04...........................00 T1 T2
0 0 N16...N8...N4...N2...N1 1 A8...A4...A2...A1 1 F16...F8...F4...F2...F1 P 1

PIOX Frame 2
H1	H2	15...............................11	10	09....................06	05	04...........................00	T1	T2
0	0	N16...N8...N4...N2...N1	1	A8...A4...A2...A1	1	F16...F8...F4...F2...F1	P	1

If the second frame indicates a dataway write operation, a third frame is transmitted as follows:

PIOX Write Frame 3

H1 H2 23...................00 T1 T2
0 1 W24(MSB) --- W1 P 1
H2 being 1 indicates a 24 bit data frame.

PIOX Write Frame 3
H1	H2	23...................00	T1	T2
0	1	W24(MSB) --- W1	P	1
H2 being 1 indicates a 24 bit data frame.

If the second frame denotes a BTR function set up [N(24)A(15)F(16)], additional third and fourth frames are transmitted as follows:

BTR Setup Frame 3

H1 H2 15...............11 10 09.......06 05 04............00 T1 T2
0 0 N16 N8 N4 N2 N1 0 A8 A4 A2 A1 0 F16 F8 F4 F2 F1 P 1

BTR Setup Frame 3
H1	H2	15...............11	10	09.......06	05	04............00	T1	T2
0	0	N16 N8 N4 N2 N1	0	A8 A4 A2 A1	0	F16 F8 F4 F2 F1	P	1

BTR Setup Frame 4

H1 H2 15.................08 07................00 T1 T2
0 1 32,768 - BTR Word Count - 1 128 - BTR Maximum No Q - 1 P 1

BTR Setup Frame 4
H1	H2	15.................08	07................00	T1	T2
0	1	32,768 - BTR Word Count - 1	128 - BTR Maximum No Q - 1	P	1

The third frame contains the NAF code that is to be repeatedly cycled by the BTR function. N must range N(0-23) and F must range F(0-7).

In the fourth frame, Word Count can range from zero to 65,535 with resultant word returns ranging from 1 to 65,536 respectively. Maximum No Q can range from 0 to 255.

AD CAMAC PIOR

The first two frames of the Port A PIOR response are always as follows

PIOR Frame 1

H1 H2 23...............16 15...........08 07..............00 T1 T2
0 1 ECHO CRATE ADDRESS STATUS BYTE 1 STATUS BYTE 2 P 1

PIOR Frame 1
H1	H2	23...............16	15...........08	07..............00	T1	T2
0	1	ECHO CRATE ADDRESS	STATUS BYTE 1	STATUS BYTE 2	P	1

PIOR Frame 2

H1 H2 23......16 15..........11 10 09............06 05 04.............00 T1 T2
0 1 STATUS BYTE 3 N16 N8 N4 N2 N1 1 A8 A4 A2 A1 1 F16 F8 F4 F2 F1 P 1

PIOR Frame 2
H1	H2	23......16	15..........11	10	09............06	05	04.............00	T1	T2
0	1	STATUS BYTE 3	N16 N8 N4 N2 N1	1	A8 A4 A2 A1	1	F16 F8 F4 F2 F1	P	1

The Crate Address and NAF data are considered as echo data. The Crate Address is generated from the T SCC address selector switch whereas NAF is directly reflected from the second PIOX transmission.

Status Byte data are as follows:

STATUS BYTE 1

7 6 5 4 3 2 1 0
Q X I BP/AIP CRLAM CRA NRA CRB

STATUS BYTE 1
7	6	5	4	3	2	1	0
Q	X	I	BP/AIP	CRLAM	CRA	NRA	CRB

Q Q indicates that a target module returned Q during a dataway cycle.
X X indicates that a target module returned X during a dataway cycle.
I I indicates the state of the Inhibit line.
BP/AIP This indicates the state of the Beam Permit/ Abort in Progress status line from the CAMAC dataway.
CRLAM This indicates if any LAM is raised in the crate.
CRA Indicates that Port A has the crate reserved.
NRA Indicates that Port A has a slot reserved.
CRB Indicates that Port B has the crate reserved.

Q	Q indicates that a target module returned Q during a dataway cycle.
X	X indicates that a target module returned X during a dataway cycle.
I	I indicates the state of the Inhibit line.
BP/AIP	This indicates the state of the Beam Permit/ Abort in Progress status line from the CAMAC dataway.
CRLAM	This indicates if any LAM is raised in the crate.
CRA	Indicates that Port A has the crate reserved.
NRA	Indicates that Port A has a slot reserved.
CRB	Indicates that Port B has the crate reserved.

STATUS BYTE 2

7 6 5 4 3 2 1 0
NRB CRBT NRBT BTA PAN=PBN PAXE NAFOKPA SR2P

STATUS BYTE 2
7	6	5	4	3	2	1	0
NRB	CRBT	NRBT	BTA	PAN=PBN	PAXE	NAFOKPA	SR2P

NRB Indicates that Port B has a slot reserved.
CRBT Indicates that CRB was terminated by a Port A operation.
NRBT Indicates that NRB was terminated by a Port A operation.
BTA Indicates that the Block Transfer function is active.
PAN=PBN Indicates that the slot currently addressed by Port A equals the last slot addressed by Port B.
PAXE Indicates a detected protocol error on the Port a PIOX line for the second or subsequent frames.
NAFOKPA Indicates that the second PIOX transmission was properly received with l's separating the NAF fields and a N that ranged between 0 and 24.
SR2P Indicates that service request level 2 was raised and permitted to cycle the dataway if appropriate. This line also indicates the acceptance of arbitration requests.

NRB	Indicates that Port B has a slot reserved.
CRBT	Indicates that CRB was terminated by a Port A operation.
NRBT	Indicates that NRB was terminated by a Port A operation.
BTA	Indicates that the Block Transfer function is active.
PAN=PBN	Indicates that the slot currently addressed by Port A equals the last slot addressed by Port B.
PAXE	Indicates a detected protocol error on the Port a PIOX line for the second or subsequent frames.
NAFOKPA	Indicates that the second PIOX transmission was properly received with l's separating the NAF fields and a N that ranged between 0 and 24.
SR2P	Indicates that service request level 2 was raised and permitted to cycle the dataway if appropriate. This line also indicates the acceptance of arbitration requests.

STATUS BYTE 3

7 6 5 4 3 2 1 0
PARDF PALDF PAN=BTNA NAFOKBT N(24)Q FAGR C Z

STATUS BYTE 3
7	6	5	4	3	2	1	0
PARDF	PALDF	PAN=BTNA	NAFOKBT	N(24)Q	FAGR	C	Z

PARDF This is the REad Data Flag for Port A and indicates that there will be a third response frame which will contain readf data or retransmitted write data.
PALDF This is the LAM Data Flag for Port A and indicates that there will nen a a third frame response which will contain the status of LAMs for slots 1 thru 24. L22 and L23 are always false.
PAN=BTNA This indicates that the slot addresses by Port A was the same slot being addressed by an active Block Transfer function. The crate controller will not have completed the requested operation.
NAFOKBT This line indicates a properly received NAF frame for the Block Transfer operation in response to a N(24)A(15)F(16) operation. Reciept of a N that ranged from 0 to 23, a F that ranged from 0 to 7, and 0's seperating the NAF fields is implied.
N(24)Q This indicates that a N(24) operation to the TSCC was executed. This line is largely irrelevant to the N(24)A(0)F(0) operation which always results in a return of LAM status.
FAGR This is the only crate controller LAM and indicates a failed Aggragate Command. This line is reset only by a Port A read of LAM status
C This indicates the state of the dataway Clear line during the last executed cycele. It is expected to be present onle during a Poiryt A induced C·S2 cycle
Z This indicates the state of the dataway Initialize line during the last executed cycle. It is expected tobe present only during a Port A induced Z·S2 cycle.

PARDF	This is the REad Data Flag for Port A and indicates that there will be a third response frame which will contain readf data or retransmitted write data.
PALDF	This is the LAM Data Flag for Port A and indicates that there will nen a a third frame response which will contain the status of LAMs for slots 1 thru 24. L22 and L23 are always false.
PAN=BTNA	This indicates that the slot addresses by Port A was the same slot being addressed by an active Block Transfer function. The crate controller will not have completed the requested operation.
NAFOKBT	This line indicates a properly received NAF frame for the Block Transfer operation in response to a N(24)A(15)F(16) operation. Reciept of a N that ranged from 0 to 23, a F that ranged from 0 to 7, and 0's seperating the NAF fields is implied.
N(24)Q	This indicates that a N(24) operation to the TSCC was executed. This line is largely irrelevant to the N(24)A(0)F(0) operation which always results in a return of LAM status.
FAGR	This is the only crate controller LAM and indicates a failed Aggragate Command. This line is reset only by a Port A read of LAM status
C	This indicates the state of the dataway Clear line during the last executed cycele. It is expected to be present onle during a Poiryt A induced C·S2 cycle
Z	This indicates the state of the dataway Initialize line during the last executed cycle. It is expected tobe present only during a Port A induced Z·S2 cycle.

The third frame of a Port A PIOR response, if present, is indicated by the assertion of PARDF or PALDF in Status Byte 3. It contains 24 bits of read data, echo write data, or LAM status.

PIOR Frame 3

H1 H2 23.................0 T1 T2
0 1 R24 - READ DATA - R1 0 1
W24 - ECHO WRITE DATA - W1
L24 - LAM STATUS - L1

PIOR Frame 3
H1	H2	23.................0	T1	T2
0	1	R24 - READ DATA - R1	0	1
W24 - ECHO WRITE DATA - W1
L24 - LAM STATUS - L1

AD CAMAC BTR

The first and last frame of a Block Transfer response is always as follows.

BTR First/Last Frame

H1 H2 23.........................16 15...13 12....8 7...4 3 2 1 0 T1 T2
1 0 CRATE ADDRESS 000 BTN16 BTN8 BTN4 BTN2 BTN1 0000 BTA BTTWC BTTNQ BTTTO P 1

BTR First/Last Frame
H1	H2	23.........................16	15...13	12....8	7...4	3	2	1	0	T1	T2
1	0	CRATE ADDRESS	000	BTN16 BTN8 BTN4 BTN2 BTN1	0000	BTA	BTTWC	BTTNQ	BTTTO	P	1

BTN Indicates the target slot of the Block Transfer operation.
BTA Indicates that the Block Transfer function is active.
BTTWC Indicates that the Block Transfer function was terminated by decrement of the desired word count to zero.
BTTNQ Indicates that the Block Transfer function was terminated by decrement of the preset maximum no Q count to zero.
BTTTO Indicates that the Block Transfer function was terminated by the TSCC because a Time Out occurred. The internal Time Out value is approximately 1/2 second.
These last four bits of status are mutually exclusive. If none is present, it is implied that the BT function was programmed off by the N(24)A(15)F(20) Port A operation. Intervening frames on the BTR line contain the read data from successful dataway operations to the target module. They are structured as follows:

BTN	Indicates the target slot of the Block Transfer operation.
BTA	Indicates that the Block Transfer function is active.
BTTWC	Indicates that the Block Transfer function was terminated by decrement of the desired word count to zero.
BTTNQ	Indicates that the Block Transfer function was terminated by decrement of the preset maximum no Q count to zero.
BTTTO	Indicates that the Block Transfer function was terminated by the TSCC because a Time Out occurred. The internal Time Out value is approximately 1/2 second.
These last four bits of status are mutually exclusive. If none is present, it is implied that the BT function was programmed off by the N(24)A(15)F(20) Port A operation. Intervening frames on the BTR line contain the read data from successful dataway operations to the target module. They are structured as follows:

BTR Data Frame

H1 H2 23..............00 T1 T2
1 1 R24 - BT DATA - R1 P 1

BTR Data Frame
H1	H2	23..............00	T1	T2
1	1	R24 - BT DATA - R1	P	1

The maximum transfer rate accommodated by Block Transfer is 750 kbyte/sec. This corresponds to a CAMAC dataway cycle every 4 microseconds. Maximum block length for BT is 65K CAMAC words. Port A and B may freely communicate with crate modules other than the BT target module throughout a Block Transfer operation.

Old AD CAMAC SLD Status Bits

Old AD CAMAC SLD Status Bits

15 14 13 12 11 10 9 8
BUSY Q_X_SRP NO_Q OP_DENIED ARBCON NO_Q_OR_X TIMEOUT LINK_ERROR

7 6 5 4 3 2 1 0
RF1CK RF2CK RF3CK CACK NAFCK EDCK PADRV CRLAM

Old AD CAMAC SLD Status Bits
15	14	13	12	11	10	9	8
BUSY	Q_X_SRP	NO_Q	OP_DENIED	ARBCON	NO_Q_OR_X	TIMEOUT	LINK_ERROR

7	6	5	4	3	2	1	0
RF1CK	RF2CK	RF3CK	CACK	NAFCK	EDCK	PADRV	CRLAM

BUSY ?
Q_X_SRP ?
NO_Q ?
OP_DENIED ?
ARBCON ?
NO_Q_OR_X ?
TIMEOUT ?
LINK_ERROR ?
RF1CK ?
RF2CK ?
RF3CK ?
CACK ?
NAFCK ?
EDCK ?
PADRV ?
CRLAM ?

BUSY	?
Q_X_SRP	?
NO_Q	?
OP_DENIED	?
ARBCON	?
NO_Q_OR_X	?
TIMEOUT	?
LINK_ERROR	?
RF1CK	?
RF2CK	?
RF3CK	?
CACK	?
NAFCK	?
EDCK	?
PADRV	?
CRLAM	?

RD CAMAC Link

RD XD

RD CAMAC XD

69 68...61 60..57 56 55 54 53 52..48 47..44 43..39 38 37 36
1 CRATE NQRETRY AUXLOCKOUT SLOT SUBADDRESS FUNCTON CP 1 1

RD CAMAC XD
69	68...61	60..57	56	55	54	53	52..48	47..44	43..39	38	37	36
1	CRATE		NQRETRY	AUXLOCKOUT			SLOT	SUBADDRESS	FUNCTON	CP	1	1

35 34..11 10 9 8 7 6 5 4 3 2 1 0
1 Write Data WP 1 1 1 1 1 1 1 1 1 1

CRATE Duh
NQRETRY If 1, repeats the function up to three times locally
AUXLOCKOUT Locks out auxillary crate processor (C1001)
SLOT N
SUBADDRESS A
FUNCTION F
CP Command Parity
WP Write data Parity

CRATE	Duh
NQRETRY	If 1, repeats the function up to three times locally
AUXLOCKOUT	Locks out auxillary crate processor (C1001)
SLOT	N
SUBADDRESS	A
FUNCTION	F
CP	Command Parity
WP	Write data Parity

RD RD

35 34..11 10 9 8 7 6 5 4 3 2 1 0
1 READ DATA RP 1 1 Q D X OFFL 0 XPE P 1

RP Read data Parity
Q Q response
D Crate LAM
X X response
OFFL Crate offline
XPE Transmit Parity error

RP	Read data Parity
Q	Q response
D	Crate LAM
X	X response
OFFL	Crate offline
XPE	Transmit Parity error

MDAT

The MDAT serial frame is 28 bits in length, self clocking, and operates at a 10 MBit per second rate. The frame consists of a two bit header, an eight bit type code, sixteen bits of data, and a two bit trailer which contains a frame parity. A signal transition always occurs at the beginning of the 100 nanosecond bit cell. A transition within the cell indicates a "1" and no transition indicates a "0". Parity is such that the frame is always 2.75 microseconds in length.

MDAT Frame Protocol

H1 H2 23..................16 15.....0 T1 T2
1 0 MSB - Type Code - LSB MSB - MDAT Data - LSB P 1

MDAT Frame Protocol
H1	H2	23..................16	15.....0	T1	T2
1	0	MSB - Type Code - LSB	MSB - MDAT Data - LSB	P	1

Frames are generally transmitted at ten microsecond intervals synchronous to TCLK event $07 (720 Hz). More detailed information concerning active frames is available in spreadsheet format.

TCLK and BSCLK

The TCLK and BSCLK serial frame is 12 bits in length, self clocking, and operates at a 10 MBit per second rate for TCLK and approximately 7.5 MBit per second for BSCLK. The frame consists of a one bit header, an eight bit event code, a parity bit, and a two bit trailer. A signal transition always occurs at the beginning of the bit cell. A transition within the cell indicates a "1" and no transition indicates a "0". TCLK bit cells are 100 nanoseconds wide and BSCLK bit cells are approximately 133 nanoseconds wide.

TCLK/BSCLK Frame Protocol

H1 7..................00 P T1 T2
0 MSB - EVENT - LSB P 1 1

TCLK/BSCLK Frame Protocol
H1	7..................00	P	T1	T2
0	MSB - EVENT - LSB	P	1	1

More detailed information concerning tclk events is available in spreadsheet format.

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