RD/EED Controls
Special Project Note 9.0
PRECISION AUTOMATIC FLUX MEASUREMENT SYSTEM (PAFMS)
Summary of Design and Simulation Results
Part 1 - Design
Mark Kozlovsky
May 13, 1993
Table of Contents
1. Introduction 3
2. System Specification 5
3. Flux Measurement Systems 6
4. Design Objectives 10
5. System Description 14
5.1 System Structure 14
5.2 Modes of Operation 18
5.3 System Implementation 20
5.3.1 System Enclosure 24
5.3.2 System Power Supply 24
5.3.3 Control Panels 27
5.3.3.a Front Panel 27
5.3.3.b Rear Panel 29
5.3.4 System Block Digram 31
5.3.5 System Software 34
6. System Components 50
6.1 Bucking Circuitry 50
6.2 Preamplifier 62
6.3 Main Amplifier 64
6.4 720 Hz Notch Filter 66
6.5 Low-Pass Filter 68
6.6 Auto Offset Compensation Circuit 70
6.7 Auto Gain Detector 74
6.8 Rectifier and V/F Converter 78
6.9 Linearity Detector 80
6.10 Zero-Crossing Detector 87
6.11 Direction Detector 93
6.12 Signal Integrator 95
6.13 VXI Interface 99
6.13.1 Register Description 99
6.13.2 ID Register 100
6.13.3 Manufacturer ID 101
6.13.4 Logical Address Register 101
6.13.5 Device Type Register 101
6.13.6 Status Register 103
6.13.7 Control Register 103
6.13.8 Offset Register 104
6.13.9 ID/Device Type Register Configuration 104
6.13.10 ID Register 105
6.13.11 Device Type Register 105
6.13.12 A16 Device Dependent Register Implementation 105
INTRODUCTORY NOTICE: This document is not intended to be the final specification for the PAFMS! Its sole purpose is to explain design ideas and to provide experimental data that verifies performance of major parts of the system. The final system specification, accompanied by specifications for each system component, will be produced during a latter phase of system development.
1. INTRODUCTION
This document presents results from the preliminary design of a Precision Automatic Flux Measurement System (PAFMS), and from PSpice simulation of those components that affect system performance.
The document defines the PAFMS overall structure as well as the structures of all system components and describes system operation.
The PAFMS is the final product developed by the RD/EED Controls Group for the MTF Waveform Capture System Project. Its development is based on the system design methodology and is aimed at solving the problem of making precise magnetic flux measurements.
All magnetic flux measurement systems may be divided into two classes:
* systems that employ analog-to-digital conversion (A/D) to obtain data for flux calculation, and
* systems that employ voltage-to-frequency conversion (V/F) for the same goal.
In turn, those systems that are based on the V/F conversion disguise themselves by using either a DC offset or signal rectification to transform the bipolar input signal into a unipolar signal that can be processed by a V/F Converter. The PAFMS uses signal rectification. Figure 1 provides a graphical representation of flux measurement system classification for representative systems.
Fig. 1 Flux Measurement System Classification.
2. SYSTEM SPECIFICATION
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AMPLITUDE
* Input signal range - 1 mV .. 10 V
* Input signal dynamic range - 80 dB
* Gain steps - 1, 2, 5, 10, 20, 50, 100, 200, 500, 1000, 2000, 5000, 10000
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FREQUENCY
* Input signal frequency range - 0.002 Hz .. 10 Hz
* System working frequency range - 0.001 Hz .. 300 Hz
* Frequency dynamic range - 110 dB
* Number of harmonics - 30 (with guaranteed sensitivity)
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NOISE
* EMI noise reduction - 80 dB
* Input signal noise reduction - 60 dB
* Internal noise reduction - 60 dB
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SYSTEM
* Number of input coils - 16
* Number of processed signals - 2
* Nonlinearity - 0.01%
* Resolution - 12 bits
* Sensitivity - 250 nV (on 1 mV processed signal)
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FLUX PROCESSOR
* Number of trigger sources - 8 (6 TTL and 2 ECL compatible)
* Resolution of the prescaler - 4 bits
* Number of synchro pulses - 255
* Synchro pulse frequency range - 0.125 Hz .. 250 KHz
* Number of encoder inputs - 2
* Encoder type - quadrature
* V/F counter size - 32 bits
* Encoder counter size - 16 bits
* Memory word size - 32 bits
* Memory block size - 32K bytes
* Memory size - 512K bytes
* Number of memory segments - 4
* Number of blocks in a segment - 4
* Number of up-down counters - 4
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INTERFACE and SOFTWARE
* Internal interface - VXI
* Communication interface - GPIB
* Software - ANSI "C" compliant
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3. FLUX MEASUREMENT SYSTEMS
Flux measurement systems are characterized by the parameters given in Table 1.
Table 1. COMPARISON OF FLUX MEASUREMENT SYSTEMS
No Parameter PAFMS Metrolab PDI 5035 DESY MTF WCS
01 Signal Amplitude 1 mV-10 V 1 mV-5 V 10 mV-10 V 10 mV-10 V
02 Amplitude Dynamic Range 80 dB 75 dB 60 dB 60 dB
03 Gain 10000 1000 1000 1000
04 Sensitivity 250 nV 500 nV 2.5 uV 2.5 uV
05 Resolution 12 11 12 12
06 Sig. Frequency 0.002 - 10 Hz - - 0.1 - 10 Hz
07 Frequency Range 0.001 - 300 Hz - - 0.01 - 200 Hz
08 Frequency Dynamic Range 110 dB - - 60 dB
09 Noise Reduction 90 dB - - 40 dB
10 Number of Coils 16 1 1 4
11 Bucking yes no no yes
12 Dynamic Offset Compensation yes no no no
13 Encoder Filtering yes no no yes
14 Programming auto/computer computer manual manual
15 Testability auto/computer partial none partial
16 Trigger Sources 8 2 1 8
17 Environment industrial lab lab industrial
18 Internal Interface VXI VME proprietary VXI
19 Communication Interface GPIB VME proprietary VXI
20 Data Access GPIB VME proprietary GPIB
More detailed list of system characteristics (originated by Miriam Bleadon) is given in Table 2.
System characterized include:
* WCS - MTF Waveform Capture System - Intermediate Prototype
* PAFMS - Final System for MTF WCS Project
* PDI 5035 - VME-based Flux Measurement System from METROLAB
* PDI 5025 - GPIB-based Flux Measurement System from METROLAB
* DESY - V/F Analog Front End from DESY
Table 2. Flux Measurement System Characteristics.
FEATURES PAFMS WCS PDI 5035 PDI 5025 DESY
Coil Configuration
Coil Inputs 16 3 1 1 1
Output Channels 2 1 1 1 1
Fractional Coil Bucking yes yes no no no
Bucking Selection software switches - - -
Amplifier/VF
Signal Amplitude 1mv - 10V 10mv-10V 5mV-5V 5mV-5V 10mV-10V
Amplitude Dynamic Range 80 dB 60dB 60 dB 60 dB 60dB
Sensitivity 250 nV 2.5 uV 2.5 uV 2.5 uV 2.5 uV
VF Resolution 12 bit 12 bit 11 bit 11 bit 12 bit
Frequency Range with Guaranteed Sensitivity 0.001 - 300 Hz 0.01 -100 Hz not specified not specified not specified
Input Signal Frequency Range 0.002 - 10 Hz 0.1 - 10 Hz not specified not specified not specified
Stages of Amplification 2 1 1 1 1
Preamplifier Gain 1,2,5,10 - - - -
Preamplifier Output Low Pass Filter Butterworth -9p - - - -
Preamplifier Output Notch Filter 720 Hz - - - -
Preamplifier Gain Selection software - - - -
Preamplifier Offset Compensation Auto - - - -
Filter poles/rolloff configurable yes - - - -
Filter configuration and selection software - - - -
Amplifier Gain 1,2,5,...1000 1,2,5,...1000 1,2,5,...1000 1,2,5,...1000 1,3,10,30,...1000
Amplifier Output Low Pass Filter Butterworth -9p Butterworth -8p Passive RC - 1p Passive RC - 1p Passive RC - 1p
Amplifier Output Notch filter 720 Hz 60 Hz - - -
Amplifier Gain Selection software switches software or switch software or switch switches
Amplifier Offset compensation Auto/Software Manual Manual None Manual
Filter poles/rolloff configurable yes no yes yes None
Filter configuration and selection software switches external capacitor external capacitor switches
Noise Reduction 90 dB 40 dB
Automatic Gain Selection Available yes no no no no
Rectification Method absolute absolute offset offset absolute
Maximum VF output frequency 1 MHz 1 MHz 1 MHz 1 MHz 500 KHz
Table 2 (continuation).
FEATURES PAFMS WCS PDI 5035 PDI 5025 DESY
Triggers
Prescale triggers yes yes yes yes -
Accept triggers from VXI yes yes yes no -
Accept TTL triggers from front yes yes yes yes -
Accept ECL triggers from front yes yes no no -
Internally Generate Triggers yes no yes yes -
Trigger on Encoder yes yes yes yes -
Encoder type quadrature quadrature quadrature quadrature -
Filter encoders to remove backlash yes yes no no -
Take timed multiple readings on triggers yes yes On encoder only On encoder only -
Maximum readings per trigger 255 255 4-on encoder only 4 -on encoder only -
Trigger setup software software software software -
Can start on encoder index pulse yes yes yes yes -
Counters
Number of Encoder channels input 2 2 1 1 -
Number of Encoder channels recorded 2 2 0 0 -
Number of VF channels input 4 4 1 1 -
Number of VF channels recorded 2 2 1 1 -
VF counter size 32 bit 32 bit 32 bit 32 bit -
Encoder counter size 16 bit 16 bit - - -
Memory
Type VME private VME private -
Number of Segments 4 4 1 1 -
Segment Size 32K x 32 bit 32K x 16 bit 8K x 32 bit 5200x32bit -
Measurements per segment 4 x 8192 4 x 4096 1 x 8192 1 x 5200 -
Interface
External Communication GPIB GPIB VME GPIB None
Internal Communication VXI Registers VXI Messages - - -
Crate VXI VXI VME Box Box
4. DESIGN OBJECTIVES
The following design objectives have been pursued during the preliminary design of the PAFMS:
* Create a system that is capable of performing two measurements simultaneously.
* Create a system that is programmable, flexible, and user-friendly, and that is automatic in the sense that it is able to extract all needed system parameters from the input signal by itself.
* Create a system that is capable of operating in a harsh industrial environment.
* Create a system that is independent of peculiarities of the mechanical systems that are used to move magnetic probes.
* Create a system that is capable of using different measurement techniques and working with a variety of magnetic probes.
* Create a system that is capable of processing input signals with very broad amplitude and frequency dynamic ranges (80 dB each):
* Amplitude - 1 mV .. 10 V
* Frequency - 0.002 Hz .. 10 Hz
* Create a system with nonlinearity in the amplifying unit less than or equal to 0.01%.
* Create a system that is sensitive to distortions on the input signal as low as 250 nV on a 1 mV input signal (12-bit resolution).
* Create a system that supports an industry standard interface to a host system and provides fast access to stored data.
To achieve these design objectives, the system employs the following:
* The amplitude and frequency dynamic ranges for both positive and negative input signals are accomplished by:
* using unipolar voltage-to-frequency conversion,
* filtering external noise before signal amplification,
* filtering internal noise before signal rectification,
* eliminating the dependency of zero-crossing detection upon characteristics of the components it employs, and
* directly connecting the rectifier to the voltage-to-frequency converter.
* System flexibility is attained by incorporating the ability to overwrite any system parameter with data from the host computer and the ability to change system configuration in order to bypass any system component.
* The system's ability to derive automatically all needed system parameters from the input signal is made possible by proprietary circuitry designed for this purpose and included in the system hardware.
* The system is isolated from the mechanical system by employing different kinds of filters to eliminate distortions in the input signal caused by jitter in both encoder and motor.
* The system communicates with the host computer via a standard GPIB interface.
* The system supports the following types of input signals:
* sine wave
* ramp wave
* staircase wave
* triangle wave
* trapezoidal wave
with the characteristics given in Table 3.
Table 3. Input signal characteristics:
Signal Period (sec) Steps Rise Time (sec) Fall Time (sec)
Sine Wave 1001010.1
Ramp Wave:positivenegative 500500 500 500
Staircase Wave 100 (for each step) 5 10 (for each step) 10 (for each step)
Triangle Wave 2004020.2 1002010.1 1002010.1
Trapezoidal Wave 50010010 50101 50101
The graphical representation of input signals is given in Figure 2.
Fig. 2. Graphical representation of input signals.
Presence of a DC offset, in the input signals, poses a question about its nature. One of the possible explanations is that this DC offset is a product of thermal EMFs caused by differences in temperature between different parts of measurement probes. This is illustrated by the diagram in Figure 3.
Fig. 3 Source of Signal Offset
5. SYSTEM DESCRIPTION
5.1 SYSTEM STRUCTURE
Functionally the PAFMS consists of the seven parts shown in Figure 4. They are:
a) Mechanical System
b) Coil Configuration Unit
c) AC Signal Amplifier
d) Signal Conversion Unit
e) Sign Detector
f) Flux Processor
g) Control and Communication Processor
Physically, the Coil Configuration Unit consists of one or more Coil Configurations Modules (CCM). The AC Signal Amplifier, the Signal Conversion Unit, and the Sign Detector are combined into the Front End Module (FEM). There can be several of such modules in the system. The Flux Processor is a Signal Integrator and Memory Module (SIM), one module per system; and the Control and Communication Processor is a commercial EPC-2 module from RadiSys Corporation. It is a VXI-based 386 Personal Computer (PC) with a 40 MByte internal hard drive, 2 MByte internal memory, and a 3.5" Floppy Drive.
The PAFMS works as follows.
Signals induced in coils, by the magnetic field of a magnet, are combined inside the Coil Configuration Unit into an input signal. This input signal is then processed by the AC Signal Amplifier.
The AC Signal Amplifier extracts an AC component from the input signal and amplifies it by a gain set either automatically by the system itself, or manually by the operator via the Control and Communication Processor.
The amplified signal is then transformed by the Signal Conversion Unit into a pulse stream whose frequency is a function of the amplitude of the amplified signal.
The Sign Detector determines the sign of the amplified signal and the precise instant when this signal is changing its polarity to produce the corresponding digital control signal Up/Down for the Flux Processor.
Fig. 4 Precision Automatic Flux Measurement System. Functional Diagram.
Both the pulse stream and the Up/Down signal are input to the Flux Processor. The latter calculates the magnetic flux by counting the number of pulses and storing the results synchronously with the incoming encoder pulses. The encoder pulses mark the positions of a probe and are produced by the Mechanical System.
The Control and Communication Processor provides the data via the GPIB interface to a host computer.
5.2 MODES OF OPERATION
There are three selectable modes of operation in the PAFMS:
* measurement
* adjustment
* test
The measurement mode is the main mode of operation. It is assumed that all system parameters have already been written and that the system configuration has already been chosen before this mode was set and the actual measurement takes place. No intervention from the service personnel - to adjust signal gain or offset, to enable or disable any of the system components, or to change coil configuration - is allowed during this mode.
The adjustment mode is primarily used to make system parameters changes. In this mode, system and coil configurations, signal type (linear or nonlinear), and system gain can be reprogrammed manually via the host computer. System gain and signal type can also be determined automatically. To do this, an adjustment run has to be performed.
This adjustment run is done once for a given probe, magnet type, and a coil configuration before the first measurement is performed. All subsequent measurements are then done without further gain and signal type adjustment. If at any time after the adjustment run has been performed, any of the components are changed, the adjustment run must be repeated. If for any reason the offset auto compensation was disabled in a chosen system configuration, then an offset adjustment has to be programmed manually.
Test mode allows the system to run with an internal signal source. It is used either to debug the system or to measure both static and dynamic system characteristics and system performance. Running the test mode requires such VXI commercial modules as Waveform Generator, Attenuator, DVM, Signal Multiplexor, Counter, and Command Module. The following system tests can be performed in test mode:
a) gain test - measures gain precision and linearity for all gain settings and both positive and negative input signals;
b) offset test - measures system offset with either a load or with the AC amplifier input shorted;
c) rectifier test - measures rectifier transfer functions for both positive and negative input signals;
d) V/F test - measures linearity of the voltage-to-frequency converter;
e) noise test - measures system internal noise with the AC amplifier input shorted and system external noise with the load shorted;
f) filter test - measures and reconstructs filter characteristics for all filters used in the system: internal low-pass and notch filters, and external filters built into input connectors;
g) direction test - measures the precision with which the sign detector works;
h) internal memory test - checks the efficiency of the system internal memory.
5.3 System Implementation
The PAFMS is constructed as a Stand-Alone VXI instrument with GPIB interface for external communications. It is shown in Figure 5 (prepared by Terry O'Brien).
All system components including the power supply and the Control and Communication Processor reside inside a standard 13-slot VXI chassis. The chassis is RF shielded and is sealed to prevent electromagnetic interference from outside sources.
All system modules are C-size VXI compliant modules with shielded covers to prevent electromagnetic interference from other modules inside the enclosure.
The chassis is provided with two panels (front and rear) to enable connections from the PAFMS to the mechanical system and to the host computer. The front panel allows the Control and Communication Processor to be connected to an external monitor, keyboard, and mouse for debugging purposes or for use of the PAFMS as a Stand-Alone system. External connections for the PAFMS are shown in Figure 6 (prepared by Terry O'Brien).
No control elements are available to the service personnel via the front and rear panels. The front panel provides visual information only about system internal status, configuration, and hazard warnings. The same information is returned to the host computer for display on the host system terminal.
The PAFMS includes the following parts:
a) Commercial VXI-bus enclosure
1. VXI RF Chassis 1261E from Racal-Dana - 1
b) Commercial VXI-bus modules
1. CPU EPC-2 from RadiSys, Inc. - 1
2. Attenuator 9920 from Cal-av Labs - 1
3. Function Generator E1340A from HP - 1
4. DVM E1410A from HP - 1
5. Relay Multiplexor E1345A from HP - 1
6. Frequency Counter E1332A from HP - 1
7. Command Module E1406A from HP - 1
All commercial modules except the CPU are used only in the test mode.
c) In-house designed and built VXI-bus modules
1. Coil Configuration Module (CCM) - 2
2. Front End Module (FEM) - 2
3. Signal Integrator and Memory Module (SIM) - 1
All in-house built VXI-bus modules use the DT-9110 VXI-bus Register-Based Interface Card from Interface Technology to do data transfer between these modules and the CPU. Made as a daughter board this card combines all of the elements necessary to implement a register-based VXI interface. The detailed description of this card is provided later in a special section.
d) In-house designed and built auxiliary non-VXI equipment
1. Front Panel - 1
2. Rear Panel - 1
Fig. 5 Precision Automatic Flux Measurement System
Fig. 6 External System Connections.
5.3.1 System Enclosure
The Model 1261E C-size VXI-bus chassis from Racal-Dana shown in Figure 7 is used as the system enclosure. It is optimized for RF applications and conforms fully to VXI-bus Specification Revision 1.4.
The chassis achieves a typical shielding effectiveness of 100 dB. It incorporates double skin construction to provide excellent attenuation of external radiation. A shielded door permits the system to be RFI sealed. Cable entries are through the front and rear panels and are fully gasketed.
Internally, the chassis' backplane connectors have beryllium copper shrouds to prevent interference between the modules and the backplane. Intermodule shields help to keep interference between modules to a minimum.
Three variable speed fans ensure sufficient cooling while preserving low acoustic noise. Air is drawn through special removable PFI proof dust filters.
The chassis contains 13 slots in the card cage, twelve of which are available for use by VXI-bus compatible instrumentation modules. The leftmost slot in the card cage is dedicated to the VXI-bus Resource Manager, a CPU EPC-2 module from RadiSys, Inc.
5.3.2 System Power Supply
System power is provided by the power supply built into the 1261E chassis. The chassis comes with a low-noise/low-ripple linear power supply which insures that chassis noise is kept to an absolute minimum.
The chassis' power supply is designed to operate at line frequencies from 45 Hz to 450 Hz and is selectable to operate at line voltages of 90-127 V and 193-253 V AC.
The chassis' power supply has the following DC capacity:
Table 4 System Power Supply
DC Voltage Peak Current Dynamic Current
+5.0 V 30 A 3 A
+12.0 V 5 A 1 A
-12.0 V 5 A 1 A
+24.0 V 5 A 3 A
-24.0 V 5 A 3 A
-5.2 V 20 A 3 A
-2.0 V 3 A 1 A
Fig. 7 The Model 1261E C-size VXI-bus Chassis
Peak-to-peak ripple/noise performance is shown in Figure 8. For the maximum load it is as follows:
* negative DC voltage - 10 mV
* positive DC voltage - 3 mV
Fig. 8 Power Supply Riple/Noise Performance.
5.3.3 Control Panels
5.3.3.a Front Panel
The front panel is shown in Figure 9. It is divided into six fields:
* system field,
* two coil configuration module fields,
* two front-end module fields, and
* SIM module field,
each of which provides visual information either about the status of the corresponding module, or about the system.
System field includes:
* connectors for a monitor, keyboard, and mouse to support the Stand-Alone mode of operation and system debugging,
* three LEDs which show system mode of operation:
* M - measurement
* A - adjustment
* T - test
* eight LEDs which show different system errors (not defined at this stage of the system development)
* indicators for the system DC power supply.
Each of the CCM fields has three LEDs which provide information about the status of CCM Outputs 1 and 2, i.e. what kind of measurements are being used (harmonic or flat), and whether their summing resistors are bypassed. It is possible to input signals into CCMs from the front panel via IN1 and IN2 terminals, and to monitor their outputs on OUT1 and OUT2 terminals. When doing this, one should realize that the voltage can be used on only one coil input at a time, so no bucking and summing operations on input signals are possible. The option of using the terminals and choosing the coil on which the signal would be tried is selectable in the test mode.
Each front end module's field includes:
* bar and digital indicators for the AC amplifier;
They show:
* output voltage from the AC amplifier;
Fig. 9 Front Panel
* offset voltage, which is set either manually or determined automatically by the system during the measurement run;
* gains on both a preamplifier and a main amplifier, which are set either manually or automatically during the adjustment run;
* the LED for offset compensation mode;
It is automatic when the LED is on and manual when it is off.
* signal characteristic LEDs:
They show:
* overload or underload on the AC amplifier when an input signal is too large or too small to be handled.
* linearity or nonlinearity of the input signal when its shape is linear or nonlinear
* distortions on the input signal when they are too big to be handled by the direction unit.
* front end direction LEDs to show directions for signal integration;
* front end configuration LEDs that show what parts of the front end circuitry are included into its current configuration.
The SIM module field includes LEDs that are identical to the LEDs on the front panel of the module itself. Their functions are described in the SIM module design specification, RD Controls Special Project Note 12.0.
The front panel is directly controlled by the CPU and is connected to its parallel port LPT2. There is no connection between the front panel and other modules except two analog signals coming from the FEMs. To display information, the CPU first reads this information from the module that has it, and then displays the information on the front panel.
5.3.3.b Rear Panel
The rear panel (shown in Figure 10) includes connectors with ferrite filters for probes, connectors for encoders, GPIB Interface and RS-232 Interface connectors, and 4 auxiliary terminals whose functions are controllable from the CPU.
Fig. 10 Rear Panel
5.3.4 System Block Diagram
Figure 11 provides a more detailed view on the system structure.
The PAFMS includes the following system components:
* Bucking Circuitry
* Preamplifier
* Preamplifier Stage 720 Hz Notch Filter
* Preamplifier Stage Low-Pass Filter
* Preamplifier Stage Auto Offset Compensation Circuitry which consists of a DC-level Detector and Signal Subtractor
* Main Amplifier
* Main Amplifier Stage 720 Hz Notch Filter
* Main Amplifier Stage Low-Pass Filter
* Main Amplifier Stage Auto Offset Compensation Circuitry which is analogous to the Preamplifier Stage Auto Offset Compensation Circuitry
* Gain Detector
* Full-Wave Rectifier
* Voltage-to-Frequency Converter
* Linearity Detector
* Zero-Crossing Detector
* Direction Detector
* Direction Trigger
* Signal Integrator
* System Controller
The Bucking Circuitry forms an input signal from the number of coil signals.
The Preamplifier conditions this signal and, if the latter is too small to be amplified only by the main amplifier, it amplifies it by the gain set either automatically by the gain detector or manually by the operator.
The Preamplifier Stage Notch Filter filters the 720 Hz component from the conditioned signal.
The Preamplifier Stage Low-Pass Filter cuts off all frequencies above 5 KHz from the conditioned signal.
The Preamplifier Stage Auto Compensation Circuitry extracts an AC component from the conditioned signal for further amplification. It compensates for both the thermal offset and the offset caused by the preamplifier and filters' circuitry.
The Main Amplifier amplifies the AC component of the input signal by the gain set either automatically by the gain detector or manually by the operator.
Fig. 11 Precision Automatic Flux Measurement System. Block Diagram.
Because the Main Amplifier can have very large gain, all undesirable components of the input signal will be amplified significantly. To get rid of these components another set of Notch and Low-Pass Filters is introduced after the Main Amplifier. Also another Auto Offset Compensation Circuit is employed to compensate for the DC offset produced by all these system components.
The Rectifier is essentially the same rectifier that is used in the DESY Front End Circuitry and in the MTF WCS Intermediate Prototype. It transforms a bipolar input signal into a unipolar one.
The V/F Converter transforms the amplified unipolar signal into a stream of digital pulses whose frequency depends on the amplitude of the amplified signal.
The Linearity Detector determines if the amplified signal is a linear signal or not. The result of this detection is used later to determine a set of threshold levels that are utilized to compare with the amplified signal in the Zero-Crossing Detector.
The Zero-Crossing Detector registers the precise moment when the amplified signal changes its polarity to reverse the direction in which the Signal Integrator counts pulses from the V/F Converter. The Zero-Crossing Detector uses two distinctive ways to detect this instant: one that is employed in the DESY Front End Circuitry, and another one which is more precise and which has been tried in the MTF WCS Intermediate Prototype. If the amplified signal has distortions so large that the higher precision detection cannot be used, then the final zero-crossing point will be determined by the lower precision circuitry.
The Direction Detector determines the direction in which the Signal Integrator counts pulses from the V/F Converter.
The Signal Integrator sums pulses from the V/F Converter and stores the results in internal memory synchronously with the incoming encoder pulses or any other trigger pulses used for the same purpose.
The System Controller programs and tests all system components of the PAFMS and communicates to the host computer. The communication is done via the GPIB Interface.
The bucking circuitry is contained in the Coil Configuration Module (CCM).
The Signal Integrator is the Signal Integrator and Memory Module (SIM).
The System Controller is a commercial EPC-2 module from RadiSys Corporation. It is a VXI based 386 PC with a 40 Mbyte hard drive and 2 Mbyte RAM.
The rest of the block diagram components constitute the Front End Module (FEM), in which components 2 through 9 form the AC Signal Amplifier shown in the system functional diagram (see fig. 4), components 11 and 12 form the Signal Conversion Unit, and components 13 through 16 form the Sign Detector.
5.3.5 System Software
This section is written by Miriam Bleadon for the MTF WCS project review and is included into this document for completeness.
SOFTWARE OVERVIEW
SOFTWARE OVERVIEW
* All code shall be ANSI C Compliant
* No system calls shall be made
* The GPIB card on the MTF Computer will be the GPIB System Controller
* The GPIB card on the EPC will behave as a passive GPIB instrument, on the MTF GPIB Bus
* All communications will originate from the MTF computer
* The MTF computer will make no real time demands on the WCS Controller
* At no time will the WCS Controller be able to interrupt the application program on the MTF computer
* All data transfer between the two computers will be as 32 bit unsigned integers
COMMUNICATION SOFTWARE ON MTF COMPUTER
The MTF application program uses 4 routines to access the WCS. These routines are provided in the WCS library, which will reside on the MTF computer. Macros will be provided to ease use. These routines are:
* WCSCommand ( unsigned int cmndcode, unsigned int param1, unsigned int param2, unsigned int param3 ) It is actually implemented as a variable argument list as WCSCommand ( unsigned int cmndcode, ...). Each command can have up to 3 integer parameters. If the parameters aren't necessary for a particular command, they can be left out.
* WCSReply ( unsigned int *intarray, unsigned int maxints, unsigned int *gotbytes, unsigned int *syserr )
* WCSInit ()
* WCSExit ()
WCS.H will have prototypes for these functions, as well as macros for the command codes and parameters
Byte swapping between Motorola and Intel orderings is built into these routines
These 4 routines make GPIB calls. The GPIB library and header file should be included in the application program
See the Documents: GPIB COMMAND INTERFACE FOR THE WAVEFORM CAPTURE SYSTEM COMMAND REVIEW FOR THE WAVEFORM CAPTURE SYSTEM
COMMUNICATION SOFTWARE ON THE EPC
The EPC is a single task DOS environment. One master program controls all WCS functions, and communicates with the external program over GPIB. It is called in autoexec.bat. It will start whenever the system is powered or rebooted.
WCSCTRL.C
* Main Program
* Parses incoming GPIB streams, and takes one of three response actions:
1. Passes command and parameters to CMND_DO ()
2. Return the output buffer contents and error codes
3. Exit program
CONTROL SOFTWARE ON THE EPC
CMND_DO ( char *cmndstr )
* Main subroutine
* Parses command code and necessary parameters out of received GPIB stream
* Checks code validity and parameter limits
* Checks instrument mode, to see if requested operation is appropriate
* Calls appropriate hardware functions in instrument libraries
* Maintains output buffer and system error status
DATA ACCESS
The V-F data is stored in the VXI SIM memory. To access this data, the application program must do the following:
1. Select which SIM to read ( 2 possible ) and the segment of memory to read (4 possible )
WCSCommand ( SIM_MEM_SEG, simboard, segment )
In response, the WCS Controller will set the appropriate register on the indicated SIM
2. Each segment stores data from 4096 measurement points. Determine the range of data to be retrieved. Specify the range by indicating the first and last point. Fetch the data. It will be returned as a byte stream.
WCSCommand ( SIM_FETC_BSTR_Q, simboard, first, last )
In response, the WCS Controller will read the indicated SIM memory. It will place all of this data in its output buffer.
3. Get the reply. Provide an integer array to hold the response byte stream. Specify the maximum number of integers that this array can hold ( at least 4*(last - first + 1 ) )
WCSReply ( &datarray[0], maxints, &gotbytes, &syserr )
In response, the WCS Controller will return its output buffer, as well as the current error conditions.
FILE ORGANIZATION ON THE EPC
\EPCONNEC
\LIB\EPCMSC.LIB Radisys EPC library
\INCLUDE EPC header files
\GPIB\C
MCIB.OBJ NI-GPIB library
DECL.H NI-GPIB header file
\VF
WCSCTRL.C WCS Controller source code
WCSCTRL.EXE WCS Controller executable
\LIB
SIM.LIB SIM library
AFG.LIB Arbitrary Function Generator library
MUX.LIB Multiplexer library
ATT.LIB Attenuator library
VXI.LIB VXI library
WCSSYS.LIB WCS System library
FILE ORGANIZATION ON THE EPC
\VF
\INCLUDE
SIMMACRO.H SIM library Macro definitions
SIMPROTO.H SIM library function prototypes
AFGMACRO.H Arbitrary Function Generator library Macro definitions
AFGPROTO.H Arbitrary Function Generator library function prototypes
MUX.H Multiplexer library Macro definitions and function prototypes
ATT.H Attenuator library function prototypes
VXI.H VXI library Macro definitions and function prototypes
SYSPROTO.H WCS System library function prototypes
WCSMACRO.H Macro definitions useful in all WCS routines and applications
\VF
\DEVICE
\SIM Source code for SIM library routines
\AFG Source code for Arbitrary Function Generator library routines
\MUX Source code for Multiplexer library routines
\ATTEN Source code for Attenuator library routines
\VXI Source code for VXI library
\SYS Source code for WCS system command and control library routines
\VF
\TEST Instrument debug and calibration programs
\MTFHOST WCS library routines and header for MTF WCS Applications
AUXILIARY SOFTWARE
* GNUPLOT Free plotting software, available on nearly all computing platforms. It is used on the PC in a windows environment, and on the MTF X-terminals. It is very handy for making simple plots of data, and known curves. It does not offer advanced curve fitting.
* FAMOS Software provided with Nicolet Oscilloscope. Provides spectral analysis of captured waveforms
* PICSURE Available on FNAL VAX. Provides plotting and curve fitting tools
DATA THROUGHPUT ON THE MESSAGE BASED SIM
While the SIM can record data very quickly, it takes quite a long time to retrieve the data from its memory. This is not hard to understand if you look at the structure of its VXI Message Based Interface Board, from ICS.
The interface has 3 registers. The first is for address and control. The second is for data input. The third is for data output. To read 16 bit data from the SIM's I/O registers or memory, the following steps must be taken:
VXIMessageSend ( select register 1 for control/address ) 3 bytes
VXIMessageSend ( send control/address data to register 1 ) 7 bytes
VXIMessageSend ( select register 3 for output ) 3 bytes
VXIMessageRecv ( read data from register 3 ) 4 bytes
TOTAL = 17 bytes
Similarly, to write 16 bit data to the SIM's I/O registers or memory, the following steps must be taken:
VXIMessageSend ( select register 1 for control/address ) 3 bytes
VXIMessageSend ( send control/address data to register 1 ) 7 bytes
VXIMessageSend ( select register 2 for input ) 3 bytes
VXIMessageSend ( send data to register 2 ) 5 bytes
TOTAL = 18 bytes
16-bit data exchanges take 4 VXI Messages. 32-bit data exchanges take 8 VXI Messages. To read a single measurement point from the SIM memory, which contains 2 16-bit values (2 Encoders) and 2 32-bit values (2 VFs) would take 24 separate VXI Messages, or 102 bytes across the backplane.
DATA THROUGHPUT ON A REGISTER BASED SIM
To read 16 bit data from the SIM's I/O registers or memory, the following steps must be taken:
VXIPeek ( register/memory address on SIM ) 2 bytes
Similarly, to write 16 bit data to the SIM's I/O registers or memory, the following steps must be taken:
VXIPoke (register/memory address on SIM ) 2 bytes
Reading 32 bit data can use the same peek and poke commands, with a different access mode. It would still take just one command. Each 32-bit data exchange would handle 4 bytes across the backplane.
To read a single measurement point from the SIM memory, which contains 2 16-bit values (2 Encoders) and 2 32-bit values (2 VFs) would take 4 separate VXIPeeks, or 12 bytes across the backplane.
For a register based board, there is an additional option for a block data transfer. This could be done with one command, to cut down on the software overhead.
ANALYZING A COMMAND
Set the SIM Trigger Source to the Front Panel TTL 1 Port
( choose SIM board 0, for right now )
Inside the MTF Application Program
WCSCommand ( SIM_TRIG_SOUR, 0, TTL_TRIGIN1 ) ;
* Recall that the arguments for this routine are implemented as a variable argument list, as
WCSCommand ( unsigned int cmndcode, ...). This routine first examines cmndcode. Embedded in the upper 16 bits is the number of parameters to expect. This key is then used to parse out the remaining parameters from the list.
* This routine then calls the function ByteSwap(), which swaps the bytes in the cmndcode and the parameters, to change from Motorola ordering to Intel ordering.
* A command bytestream is formed. The first byte is the letter 'W'. The remaining bytes are the cmndcode, followed by each of the parameters. When the EPC sees the first byte, it will know that a command is being written. It will then wait for the command, and the parameters.
* The entire bytestream is then fed to ibwrt(), the GPIB writing function supplied in the GPIB library from National Instruments. The entire bytestream is written with this one command. It puts the data on the bus, one byte at a time, until all of the bytes have been sent.
ANALYZING A COMMAND
Inside the EPC WCSCTRL Program
The WCS is a passive device on the GPIB. It waits to be told what to do. If it is done with its previous job, it just sits and waits on the bus, until the bus controller addresses it to listen for incoming data.
* wcsctrl.c waits on the bus until addressed to listen. It uses the ibwait() function from the GPIB library from National Instruments
* When addressed to listen, it uses the ibrd() function to accept all incoming data, until released by the bus.
* Once released, it starts to parse the bytestream. The program checks the first byte. It sees the letter 'W. That means that the remainder of the bytestream is a command with some parameters. It strips off the 'W', and sends the remaining string to cmnd_do ( char *cmndstring )
* cmnd_do ( char *cmndstring ) reads the first 32 bits. This should be the command code. It checks to see if it is a valid code. If not, it sets an error flag and returns. It sees the command code SIM_TRIG_SOUR. It knows that this takes two parameters, and they are parsed out of the string.
* The routine checks the parameters, making sure they are within the limits. If not, it returns and sets an error flag.
* The routine checks the operating mode of the SIM. If a self-test or measurement is underway, it will not change the trigger source. It sets an error flag and returns.
* The appropriate routine from the SIM library is then called, trgsour ( 0, TTL_TRIGIN1 )
* It checks the return status from trgsour( ). If it failed, it sets an error flag.
* Control is returned to the main program. wcsctrl.c again waits on the GPIB bus, until told what to do.
ANALYZING A COMMAND
Inside trgsour( 0, TTL_TRIGIN1 )
* There is a 16 bit register on the SIM which holds several parameters used to set up the trigger. The trigger source is just one of these parameters, and is stored in Bits 0-2 of this register. The other bits should not be touched. The first thing to do is to read the old value in the register. Use rdio(0, TRG_ADDR, &oldtriggerstuff).
* rdio ( 0, TRG_ADDR, &oldtriggerstuff ) formulates the control bits that need to be sent to the control/address register on the SIM. These bits tell the SIM message interface that we want to read data from the board. These bits are sent to wrcsr( 0, csr )
* wrcsr( 0, csr ) formats and sends two VXI messages to the SIM interface board. It first looks up the VXI name for the indicated SIM board, in this case, board 0. Its VXI name, as registered with the VXI resource manager happens to be "ics". The first message it sends to "ics" tells the interface to select its first register. This is the CSR. The second VXI message holds the data for the CSR. The VXI messages are sent with VXIMessageSend( "ics", command_message, number_bytes_to_send ). In turn, this routine formats the appropriate command string to be sent to the EPC routine, which actually accesses the VXI backplane. The routine that is called is part of the EPC Message Delivery System, MDSChainSend( devicename, buffer, 0 ).
* We are back in the rdio() routine. At this point, we have successfully told the SIM interface that we want to get data from the SIM. To get the data from the interface, use getdata ( 0, &buffer ).
* getdata ( 0, &buffer ) sends a VXI Message to the "ics" board, telling it to select register 3 on the interface. This message is sent with VXIMessageSend() and MDSChainSend (). We now read the response using VXIMessageRecv(), which calls MDSReceiveMessage().
ANALYZING A COMMAND
* We are back in the trgsour() routine. We have successfully read the old value in the register. It took 3 messages sent over the backplane, and one received. We now store the new trigger source selection in Bits 0-2, without affecting the other Bits. It is now time to put the new value into the SIM. For this, we call on
wrio( 0, TRG_ADDR, newtriggerstuff )
* wrio( 0, TRG_ADDR, newtriggerstuff ) formulates the control bits that need to be sent to the control/address register on the SIM interface. These bits tell the message interface that we will be writing data to the board. These bits are sent with wrcsr ( 0, csr ). Recall that this routine has to send 2 VXI messages, using VXIMessageSend() and MDSChainSend (). We now need to put the data on the SIM. Use putdata ( 0, buffer ).
* putdata ( 0, buffer ) sends a VXI Message to the "ics" board, telling it to select register 2 on the interface. This message is sent with VXIMessageSend and MDSChainSend (). We now get to send the data to the interface. Again we use VXIMessageSend and MDSChainSend()
* trgsour() is now completed. It took 4 VXI Messages to get the old value of the trigger register, and it took 4 VXI Messages to write the new value of the trigger register. If there was a failure in any of these routines, trgsour() would return with a failed status.
6. SYSTEM COMPONENTS
The following system components are going to be considered in this chapter:
* Bucking Circuitry
* Preamplifier
* Main Amplifier
* Notch Filters
* Low-Pass Filters
* Auto Offset Compensation Circuits
* Auto Gain Detector
* Rectifier and V/F Converter
* Linearity Detector
* Zero-Crossing Detector
* Direction Detector
* Signal Integrator.
6.1 Bucking Circuitry
The Bucking Circuitry incorporates 16 identical coil configuration channels, each of which has a structure shown in Figure 12.
The coil configuration channel includes three groups of relays:
* polarity relays
* selection relays
* bucking relays
and a programmable bucking potentiometer BuckR that allows the user to vary the amount of current used to buck the currents induced into signal coils. The total number of relays in one coil configuration channel is 8.
Relays from one group work in parallel; they turn on and off simultaneously. One control signal is employed to control the work of such a group. There are three control signals for each coil configuration channel:
* Pol - to control the polarity relays
* Sel - to control the selection relays
* Buck - to control the bucking relays
The Bucking Circuitry uses latched relays. This means that the circuitry has to provide two control signals to turn each of them on and off. Thus, the following six signals are actually used to control each coil configuration channel:
* PolOn, PolOff - to control the polarity relays
* SelOn, SelOff - to control the selection relays
* BuckOn, BuckOff - to control the bucking relays
Fig. 12 Coil Configuration Channel
Each coil configuration channel provides three possible configurations for the coil connected to it. The coil may be used either as a harmonic coil, a flat coil, or as a bucking coil. In any of these configurations, the coil may be connected either in forward or reverse polarity.
To configure a coil one must use the following configuration table:
Table 5. Coil configuration table
Coil Configuration Group of relays
Polarity Selection Bucking
Harmonic Forward off off does not matter
Reverse on off does not matter
Flat Forward off on off
Reverse on on off
Bucking Forward off on on
Reverse on on on
Each coil configuration channel has 6 outputs for chaining channels with each other. They are:
* Harm_In, Harm_Out - for the harmonic coil configuration
* Flat_In, Flat_Out - for the flat coil configuration
* Buck_In, Buck_Out - for the bucking coil configuration.
Physically, the bucking circuitry is built from two Coil Configuration Modules, each of which includes eight coil configuration channels. This is shown in Figure 13. To ensure that any coil connected to one of the modules can be used in coil configuration of the other module, each Coil Configuration module provides three output signals Harm, Flat, and Buck.
The internal connections to the coil configuration channels are shown in Figure 13. The Harm_Out, Flat_Out, and Buck_Out outputs of each preceding channel are connected to the Harm_In, Flat_In, and Buck_In outputs of the successive channel. The Harm_In, Flat_In, and Buck_In outputs of the first channel serve as one leg of the module's Harm, Flat, and Buck outputs, and the Harm_Out, Flat_Out, and Buck_Out outputs of the last channel serve as the other leg of these module's outputs.
It is possible to use just one or two Coil Configuration modules to form the Coil Configuration Unit. The latter has two outputs to do harmonic and flat coil measurements simultaneously: Output 1 and Output 2. Each of these outputs can be configured to work either with or without bucking and either with or without a summing resistor (RsumH and RsumF accordingly). A group of relays is added to bypass these resistors: summing relays. They are controlled by the signals SumHOn, SumHOff, SumFOn, and SumFOff correspondingly.
Several ways of connecting modules to each other and choosing signals for Outputs 1 and 2 to form different variations of the Coil Configuration Unit are shown in Figures 14.a through 14.g.
One must realize that bucking can be used only for harmonic measurements. There is no provision for using coils configured as the bucking coils for flat coil measurements in the proposed Bucking Circuitry.
Fig. 13 Coil Configuration Channel Interconnections
Fig. 14.a Coil Configuration Module Interconnections. Stand-Alone Mode.
Fig. 14.b Coil Configuration Module Interconnections. Stand-Alone Mode.
Fig. 14.c Coil Configuration Module Interconnections. Combined Mode.
Fig. 14.d Coil Configuration Module Interconnections. Combined Mode.
Fig. 14.e Coil Configuration Module Interconnections. Combined Mode.
Fig. 14.f Coil Configuration Module Interconnections. Combined Mode.
Fig. 14.g Coil Configuration Module Interconnections. Combined Mode.
6.2 Preamplifier
The preamplifier circuitry is shown in Figure 15. It includes:
* preamplifier U1
* output buffer U2
* differential shield drivers U3, U4
* gain and test control relays
* input connector
The preamplifier is built around the instrumentation amplifier AD-624 from Analog Devices anf is used in the differential mode of operation. Diodes D1..D4 provide protection for the amplifier inputs against voltage spikes on signal wires. Resistors R1 and R2 provide paths to ground for the amplifier input bias currents, otherwise the amplifier would saturate.
Four test control relays implement two test modes for the preamplifier: test with grounded inputs (GIT) and test with shorted inputs (SIT). When the GIT is performed the GIT relays are on and SIT relays are off; for the SIT they are vice versa. During the measurement mode, the GIT relays are always on, and the SIT relays are always off. The SIT relays also have to be turned on when adjustment of the preamplifier's input and output offsets needs to be done.
The differential shield driver improves AC common-mode rejection when shielded cable is used to minimize noise. The main purpose of a shielded guard is to reduce voltage across the cable's leakage resistance between the shield and the signal wire. The rule of thumb for shielded guard is that there must be no noise voltage applied to the guard. In noisy systems, capacitively coupled noise will be differentiated, emphasizing the higher-frequency components. This can be avoided by using a buffer with fast response and low output impedance. The dual precision, high speed BiFET amplifier AD-712 from Analog Devices, for instance, can be used for this purpose. The OP-77 amplifiers shown in fig. 15 are used in the schematic only for illustrative purpose. The final design will use an AD-712.
The preamplifier provides four gains: 1, 2, 5, and 10. Selection of any one of these gains is controlled by three gain relays: "Gain 2", "Gain 5", and "Gain 10". For Gain 1, all relays are off; for any other gain the corresponding relay is on and all others are off.
Potentiometers R9 and R14 are used to adjust the preamplifier input and output offsets. Potentiometer R18 adjusts an offset on the output buffer.
Fig. 15 Preamplifier. Circuit Diagram.
6.3. Main Amplifier
The main amplifier circuitry is very similar to the preamplifier circuitry and uses the same instrumentation amplifier AD-624 from Analog Devices, but in the single-ended mode of operation.
The circuitry includes the amplifier U1, buffer amplifier, and 11 gain relays ("Gain 2, 5, 10, 20, 50, 100, 200, 500, and 1000") that control the amplifier's gain.
The main amplifier provides 10 selectable gains. Gains are selected by controlling the gain relays according to Table 6. Gains 1 through 50 require external resistors to specify gain, and gains 100 trough 1000 rely on the internal amplifier's gain resistors. Potentiometers R1 trough R5 are used to adjust gains from 1 to 50.
Table 6. Main Amplifier Gain Selection
Gain Gain Relays
2 5 10 20 50 100 200 500 1000
1 OFF OFF OFF OFF OFF OFF OFF OFF OFF
2 ON OFF OFF OFF OFF OFF OFF OFF OFF
5 OFF ON OFF OFF OFF OFF OFF OFF OFF
10 OFF OFF ON OFF OFF OFF OFF OFF OFF
20 OFF OFF OFF ON OFF OFF OFF OFF OFF
50 OFF OFF OFF OFF ON OFF OFF OFF OFF
100 OFF OFF OFF OFF OFF ON OFF OFF OFF
200 OFF OFF OFF OFF OFF OFF ON OFF OFF
500 OFF OFF OFF OFF OFF OFF OFF ON OFF
1000 OFF OFF OFF OFF OFF OFF OFF OFF ON
Potentiometers R12 and R17 are used to adjust the amplifier input and output offsets. Potentiometer R19 adjusts an offset on the output buffer.
Fig. 16 Main Amplifier. Circuit Diagram.
6.4. 720 Hz Notch Filter
The 720 Hz Notch Filter, whose PSpice schematic diagram is given in Figure 17, is a continuous ten-pole Butterworth notch filter with the Akeberg-Mossberg circuit implementation. It has the following parameters that were defined to provide an output signal flatness of 0.0002 dB for the entire system frequency range (0.001 Hz .. 300 Hz):
* Lower Pass Band Cutoff Frequency - 620 Hz
* Lower Stop Band Cutoff Frequency - 700 Hz
* Upper Stop Band Cutoff Frequency - 740 Hz
* Upper Pass Band Cutoff Frequency - 820 Hz
* Pass Band Ripple - 3 dB
* Stop Band Attenuation - 60 dB
* Gain - 0 dB
The filter was designed using the Filter Design CAD from Microsim Corp. The complete design report produced by this program is given in Appendix A.
The following factors were considered in the notch filter design:
* Allowable variations of the power line frequency
* Filter size
* Ratio between Q factor and desirable attenuation
Variations in the power line frequency determine the stop band bandwidth; filter size limits the choice of possible Q factors; and ratio between Q and gain should be chosen in such a way that neither filter size nor the filter attenuation would suffer.
All properties of the filter are described in the PSpice simulation results section of this document.
Fig. 17 720 Hz Notch Filter
6.5 Low-Pass Filter
The Low-Pass Filter is a continuous 9-pole Butterworth filter with the Sallen-Key circuit implementation. Its PSpice schematic diagram is shown in Figure 18. The filter has the following parameters that were defined to provide an output signal flatness of 0.0002 dB for the entire system frequency range (0.001 Hz .. 300 Hz):
* Number of poles - 1, 3, 9
* Number of programmable configurations - 3
* Type - continuous
* Circuit implementation - Sallen-key
* Pass Band Cutoff Frequency - 5 KHz
* Stop Band Cutoff Frequency - 11 KHz
* Pass Band Ripple - 3 dB
* Stop Band Attenuation - 60 dB
* Gain - 0 dB
Two additional outputs (from the first and the third poles) are added to the filter to provide programmability of its frequency response. The filter's outputs (Pole 1, Pole 3, and Pole 9) are further multiplexed into one filter output via tree relays of the same type that is used in the bucking circuitry. These relays are controlled by the system controller, thus providing the user with the ability to choose from three possible filter configurations.
The filter was designed using the Filter Design CAD from Microsim Corp. The complete design record produced by this program is given in Appendix B.
All properties of the filter are described in the PSpice simulation results section of this document.
Fig. 18 Low-Pass Filter.
6.6 Auto Offset Compensation Circuit (AOC)
The AOC cancels the DC component from the composite amplified signal, thus, eliminating the need for manually adjusting signal offsets caused by thermal EMFs and the AC signal amplifier components. The AOC consists of a DC Level Detector and a Subtractor.
The block diagram of the DC level detector is shown in Figure 19. The DC level detector includes two identical circuits, each of which consists of an AC Buffer, a Phase Shifter, and a Subtractor. The first circuit forms a DC Compensator; the second - an Error Compensator.
Each of the circuits works as follows:
AC component of the composite (AC + DC) input signal is determined by the AC buffer. The latter introduces a large phase shift into it. To eliminate this phase shift, the input signal's phase is shifted by the phase shifter and then the AC signal is subtracted from the shifted composite signal. Phase shift transfer functions for both the AC buffer and the phase shifter are designed to be identical, so the result of the subtraction is close to an ideal DC signal as can be seen from the following equation:
(DC + AC shifted) - AC shifted = DC.
The need for the error compensator comes from the fact that it is very hard to tune the phase shift transfer functions of the AC buffer and the phase shifter to the degree that they become identical for very low frequencies. To make them identical, one must use very large capacitors. But large capacitors have large leakage currents and low resistance which limit their use. Also the size of such capacitors makes their presence on a PC board impractical. By cascading two circuits in series one can achieve acceptable results without the use of large capacitors since the second circuit would be working with a much lower AC component than the first one.
The DC Level Detector has the following characteristics:
* Composite input signal amplitude - * 10 V
* Offset in composite input signal - * * 10 V
* Input signal frequency range - 0.002 .. 300 Hz
* Offset frequency range - < 0.002 Hz
* Nonlinearity of the DC output signal - 0.02 % on *10 V input signal
* Response time - * 30 minutes
Figure 20 is the PSpice circuit diagram for the DC level detector. All properties of this circuitry are described in the PSpice simulation result section of this document.
Fig. 19 DC Level Detector. Block Diagram.
Fig. 20 DC Level Detector. Circuit Diagram.
6.7 Auto Gain Detector
The Auto Gain Detector (AGD) takes one output signal from the preamplifier and one from the main amplifier, analyzes them, and produces gain control signals that turn on or off corresponding gain relays on the preamplifier and the main amplifier.
The AGD is controlled by the system controller, meaning that gain settings can be read or written by it. The system controller also enables or disables the functioning of the AGD.
The AGD's block diagram is shown in Figure 21. It includes two low frequency peak detectors, a 16-bit digital-to-analog converter (DAC), a comparator block, and a gain controller.
The peak detectors are needed to register only the highest amplitudes on both amplified signals. This prevents system overloading caused by higher than needed gains. There is no special requirement for how well they must operate, because one more digital peak detector is incorporated into the gain controller. This digital peak detector eliminates errors from the analog peak detectors caused by discharge of the sample-and-hold capacitors during very slow input signals. This combination of analog and digital peak detectors produces less ringing on digital lines, and at the same time provides the highest probability of detecting the correct amplitude.
The comparator block accepts three analog signals from two peak detectors and the DAC, and produces logical signals that show which voltage interval the amplified signal operates in. Its block diagram and the algorithm for determining the operating interval are shown in Figure 22.
The comparator block includes two analog comparators that compare signals from the peak detectors to a voltage level produced by the DAC; two 8-bit shift registers that store comparison results by shifting them each time when the shift signal comes from the gain controller; and logic to determine the voltage interval that the amplified signal falls into. Corresponding to each interval, gain values for the preamplifier and the main amplifier are given in the table shown on the left side in Figure 22.
The comparator block generates error signals in the cases when the input signal is either too small or too large. By reading these signals, the system controller is able to alert the user about such occurrences.
The gain controller communicates to the system controller and transforms interval signals from the comparator block to gain settings for both the preamplifier and the main amplifier. It also controls the ADC and produces the shift signal for the comparator block. The gain controller has a built-in digital peak detector, so it remembers only the highest value of a signal operating interval. This peak detector consists of an interval 8-bit register and an interval 8-bit comparator.
The gain detector accepts amplified signals in the range from 1 V to 10 V. It works as follows.
As soon as the system controller enables the gain detector, the gain controller performs the following sequence of activities:
1. sets the ADC to 1 mV output voltage
2. produces the shift signal
3. sets the ADC to 10 mV output voltage
4. produces the shift signal
5. sets the ADC to 50 mV output voltage
6. produces the shift signal
7. sets the ADC to 100 mV output voltage
8. produces the shift signal
9. sets the ADC to 500 mV output voltage
10. produces the shift signal
11. sets the ADC to 1 V output voltage
12. produces the shift signal
13. sets the ADC to 5 V output voltage
14. produces the shift signal
15. sets the ADC to 10 V output voltage
16. produces the shift signal
17. compares operating interval in the interval register with the current one produced by the comparator block
18. writes the current interval into the interval register if it is larger than the one that was written into this register either during the previous sequence of activities or during the system setup procedure
19. encodes gain settings according to the table given in Figure 22 and stores them in built-in gain registers
20. stores the error signals from the comparator block into a built-in status register.
This sequence of actions is repeated by the gain controller until the gain detector is enabled. It is the responsibility of the system controller to know when the gain detector must be disabled.
When the gain detector is disabled, the system controller is able to read data from or to write data into all gain controller internal registers. This allows manuall overwrite of gain settings if it is desirable, diagnosis of the gain detector performance, and read back of internal register settings.
Fig. 21 Auto Gain Detector. Block Diagram.
Fig. 22 Comparator Block. Algorithm and Block Diagram.
6.8 Rectifier and V/F Converter
The rectifier and V/F converter together form the signal conversion unit which is shown in Figure 23. It consists of
* input buffer U1
* full-wave rectifier U2 .. U4
* sign output buffer U5
* V/F converter AD-652 from Analog Devices U6
* 2 MHz oscillator U7.
For a positive input signal, diode D1 is opened, and U2 works as a simple unity-gain follower. For a negative input signal, diode D1 is closed, and U4 tries to keep the positive input of U2 at virtual ground. This turns U2 into a unity-gain inverter. Thus, the signal on the output of the U2 is always positive.
The V/F converter takes this signal and transforms it into a stream of digital pulses whose frequency depends on the amplitude of the rectified signal. The V/F is clocked by a 2 MHz signal from oscillator U7 to assure both its maximum linearity and the system maximum resolution at the same time.
Fig. 23 Signal Conversion Unit. Circuit Diagram.
6.9 Linearity Detector
The linearity detector determines if the incoming signal is linear or nonlinear. It does this during an adjustment run. The result is used in the zero-crossing detector to set appropriate threshold levels for the zero-crossing comparators.
The linearity detector block diagram is shown in Figure 24 and its time diagram in Figure 25. The linearity detector includes:
* 8-channel 14-bit DAC with an external +5 V voltage reference
* comparator circuit
* eight digital delays
* linearity controller
* counter
* threshold register
* digital comparator
* linearity trigger.
The 8-channel DAC is programmed to produce the following voltages:
Level 1 (L1) = + 0.6 V
Level 2 (L2) = + 0.7 V
Level 3 (L3) = + 0.8 V
Level 4 (L4) = + 0.9 V
Level 5 (L5) = - 0.6 V
Level 6 (L6) = - 0.7 V
Level 7 (L7) = - 0.8 V
Level 8 (L8) = - 0.9 V.
These values are chosen to include nonlinear parts of the lowest possible sine wave input signal, i.e. the signal with peak amplitudes at * 1 V (see Fig. 25).
The comparator circuit includes 8 analog comparators to compare an input signal with L1 .. L8, and one more analog comparator to compare this signal with zero volt. The latter determines the sign of the input signal. When a comparator determines that the input signal is larger (by absolute value) than its reference voltage, it produces the logical 1 signal, i.e., its output goes high, and vice versa.
The digital delays are used to filter noise on comparator outputs caused by the jitter in the mechanical system. The delay of 0.2 sec helps to filter noise at the beginning of the input signal. All other delays (of 0.8 msec) filter noise between subsequent levels L1 .. L8 of the input signal.
Fig. 24 Linearity Detector. Block Diagram.
Fig. 25 Linearity Detector. Timing Diagram.
The linearity controller uses the ordering of high comparator outputs to determine the order in which comparator outputs have to be examined for linearity. It does this by using Table 8, where table entries 1 .. 4 represent the order in which the corresponding comparator ouputs L1 .. L8 occur or will be analyzed. Section 2 in Table 8 represents different order combinations in which comparator outputs go high, and Section 3 shows the corresponding orders which will be used for linearity analysis.
The linearity controller produces three signals: Reset, Start, and Direction (Dir) that control the work of the counter. The counter counts clock pulses up or down depending on the direction signal. It starts counting on the start signal. The reset signal sets the counter to zero and is always produced before the start signal. It is a function of the order in which the comparator outputs go high and the sign signal shown in Section 1 of Table 8. To produce the start and direction signals, the linearity controller uses those comparator outputs which have been selected for the linearity analysis. The start signal always starts with the comparator output which corresponds to table entry 1 and finishes with the comparator output which corresponds to table entry 4. The direction signal is set to logical 0 by the reset signal and it toggles with each comparator signal that corresponds to table entries 1 through 4 (see Fig. 25).
The linearity detector works as follows.
The system controller sets the threshold register to a pre-calculated value "Threshold" that is determined from the following empirical equation
where
t(L1 - L2) - time interval between L1 and L2 levels on the ideal sine wave signal with a peak-to-peak amplitude of 2V and with zero offset;
t(L2 - L3) - time interval between L2 and L3 levels on the ideal sine wave signal with a peak-to-peak amplitude of 2V and with zero offset;
t(L3 - L4) - time interval between L3 and L4 levels on the ideal sine wave signal with a peak-to-peak amplitude of 2V and with zero offset;
fclock - internal clock frequency.
It is easy to see that for a linear signal this equation will produce Threshold = 0 and that for any nonlinear signal the Threshold would be >> 0.
The system controller then programs the 8-channel DAC to produce voltages L1 .. L8 and resets the counter and linearity trigger. After this is done, the system controller sets the run signal high (not shown in Fig. 24 because the interface circuit is buried inside the linearity controller's internal logic). This signal enables the detection process for the duration of the adjustment run. The system controller sets the run signal low when the adjustment is over.
During the detection process the linearity controller looks to match the sequence of comparator outputs with one of those defined in Section 2 of Table 8. The beginning of this sequence is determined by the first event to occur, i.e., by the first comparator output that goes high. Any subsequent comparator output from the sequence is analyzed only after the delay corresponding to it ends, i.e., L1 is analyzed after L8D, L2 - after L1D, L3 - after L2D, L4 - after L3D, etc. This is done to filter noise on the input signal caused by the jitter in the mechanical system. If none of the sequences have been found during the run, but the comparator outputs have changed, then the error signal "Noise too large" is produced by the linearity controller to inform the system controller that linearity detection cannot be accomplished. If none of the sequences have been detected and none of the comparator outputs have changed during the run, then another error signal "Signal too small" is produced for the same purpose.
When a sequence match from Section 2 of Table 8 has been found, the linearity controller issues the reset signal and starts looking for the corresponding sequence of the comparator outputs from Section 3 of Table 8. If this sequence cannot be found, the linearity controller will produce the "Noise too large" error signal.
When the first comparator output from the desired sequence goes high, the linearity detector issues the start signal and sets the direction signal to count up. The direction signal will be toggled by each comparator output from the sequence.
With the start signal high, the counter starts counting internal clock pulses up or down depending on the state of the direction signal. The digital comparator compares the contents of the counter with the threshold kept in the threshold register. After the start signal ends, the linearity detector issues the set signal which writes the state of the digital comparator output into the linearity trigger.
Table 8.
Section 1 Section 2 Section 3
Sign Sequence of Comparator Signals Sequence of Comparator Signals for Linearity Analysis
Pos Neg L1 L2 L3 L4 L5 L6 L7 L8 L1 L2 L3 L4 L5 L6 L7 L8
X - 1 2 3 4 - - - - 4 3 2 1 - - - -
X - - 1 2 3,4 - - - - - - - - 1 2 3 4
X - - - 1,4 2,3 - - - - - - - - 1 2 3 4
X - - 4 3 1,2 - - - - - - - - 1 2 3 4
X - 4 3 2 1 - - - - - - - - 1 2 3 4
X - 3 2 1 - 4 - - - - - - - 4 3 2 1
X - 2 1 - - 3 4 - - - - - - 4 3 2 1
X - 1 - - - 2 3 4 - - - - - 4 3 2 1
- X - - - - 1 2 3 4 - - - - 4 3 2 1
- X - - - - - 1 2 3,4 1 2 3 4 - - - -
- X - - - - - - 1,4 2,3 1 2 3 4 - - - -
- X - - - - - 4 3 1,2 1 2 3 4 - - - -
- X - - - - 4 3 2 1 1 2 3 4 - - - -
- X 4 - - - 3 2 1 - 4 3 2 1 - - - -
- X 3 4 - - 2 1 - - 4 3 2 1 - - - -
- X 2 3 4 - 1 - - - 4 3 2 1 - - - -
This is illustrated by the timing diagram in Fig. 25. It shows the case when the starting sequence is L1, L2, L3, and L4, and the linearity sequence is L4, L3, L2, and L1, which corresponds to the first line of Table 8.
6.10 Zero-Crossing Detector
The zero-crossing detector determines the precise instant when the amplified signal changes its polarity. It issues a zero-crossing pulse at that very moment in order to signal to the direction detector that it is time for the signal integrator to start counting pulses from the V/F converter in the opposite direction.
What sets this particular zero-crossing detector apart from all existing detectors, is that it is not trying to find a zero point by looking at the signal itself, but rather predicts it by making the assumption that any signal processed by the system, linear or nonlinear, is linear near zero.
Figure 26 provides the block diagram for the zero-crossing detector, and Figure 27 shows its timing diagram.
The zero-crossing detector includes:
* 8-channel 14-bit DAC with an external +5 V voltage reference
* block of eight analog comparators
* four digital delays
* zero-crossing controller
* five counters
* block of four digital comparators whose outputs are logically combined by the AND function
* bad signal trigger
The 8-channel DAC is programmed to produce the following voltages:
Level 1L (LL1) = + 0.30 V
Level 2L (LL2) = + 0.20 V
Level 3L (LL3) = + 0.15 V
Level 4L (LL4) = + 0.10 V
Level 1N (LN1) = + 0.12 V
Level 2N (LN2) = + 0.08 V
Level 3N (LN3) = + 0.06 V
Level 4N (LN4) = + 0.04 V.
Levels from LL1 to LL4 are used for linear signals, and levels from LN1 to LN4 - for nonlinear signals. Only levels LL1 and LN1 must be defined; all others are derived using the following equations:
Fig. 26 Zero-Crossing Detector. Block Diagram.
Fig. 27 Zero-Crossing Detector. Timing Diagram.
Levels for linear signals are chosen larger than levels for nonlinear signals because it is easier to work with larger levels than smaller ones. It is impossible to use these levels for nonlinear signals because they have to be closer to zero to satisfy the linearity requirement near the zero point.
The comparator circuit includes 8 analog comparators to compare a rectified input signal with the levels LL1 .. LL4 and LN1 .. LN4. When a comparator determines that the input signal is above its reference voltage, it produces the logical 1 signal. In the case when the input signal is smaller than the reference voltage, the comparator output goes to logical 0 level.
Comparator outputs LL1 .. LL4 are multiplexed with the LN1 .. LN4 comparator outputs to form signals L1 .. L4. The choice of outputs that are used to form these signals depends on the state of the Linear/Nonlinear line. If it is in Linear state, then outputs from linear comparators are chosen, if this input is in Nonlinear state, then outputs from the nonlinear comparators are used for the same purpose.
The zero-crossing controller originates control signals (Count and Direction) for the five counters. The start signal for the first counter starts with the L1 signal (see Fig. 27) and ends with the Zero-Cross signal from the fifth counter. Its direction signal is toggled by the L1 and L2 signals. The start signal for the second counter starts with the L2 signal and ends with the L4. Its direction signal is toggled by the L2 and L3. The start signal for the third counter starts with the L2 and ends with the Zero-Cross. Its direction signal is toggled by the L2 and L4. The start signal for the fourth counter starts with the L1, then ends with the L2, then starts again with the L4 and ends again with the Zero-Cross. Its direction signal is toggled by the L1 and L2. The start signal for the fifth counter starts with the L1 and ends with the Zero-Cross. Its direction signal is toggled by the L1 and L3 signals.
The first four counters serve as signal linearity checkers, and the fifth one produces the zero-crossing pulse. Counter 1 checks signal linearity in the intervals L1-L2 and L2-L4; Counter 2 - in the intervals L2-L3 and L3-L4; Counter 3 - in the intervals L2-L4 and L4-0; and Counter 4 - in the interval L1-L2 and L4-0.
They check linearity by measuring differences between the lengths of their pair of intervals. For ideal linear signals, these differences have to be equal zero. The work of this detector is based on the assumption that these differences must be less than some threshold. If the difference in any counter is larger than the threshold, then this indicates that there is some kind of distortion on the input signal. This prevents the zero-crossing detector from making a safe prediction of where the zero-point can be located.
In this case the bad signal trigger is set to the bad signal state to inform the direction detector that other means must be employed in order to determine the actual zero-crossing point. When the counters indicate that the input signal is linear on all intervals, the bad signal trigger is switched into the good signal state.
The predicted zero-crossing point is then determined by extrapolating signal function on the interval L1-L3 to the point where it crosses zero. The extrapolation is done by Counter 5 by counting clock pulses up during the L1-L3 interval and then counting them down to zero after this interval ends.
Any of the digital comparator outputs goes high when the contents of the corresponding counter becomes smaller than its threshold value. This latter is an empirical value and will be determined during the system test. The rule of thumb is that it is 4 times larger than the number that represents signal nonlinearity near zero. Assuming that this nonlinearity is 0.1%, that maximum signal frequency is 10 Hz, and that the minimum amplitude is 1 V, we get the following empirical expression for the minimum value of threshold:
With , Threshold = 4.
The zero-crossing detector works as follows (refer to the timing diagram in Fig. 27).
The system controller sets the threshold value and resets all counters and the bad signal trigger. This is done inside the zero-crossing controller.
When the input signal starts decreasing toward zero volts, the analog comparators produce a sequence of signals L1 .. L4. These signals are analyzed by the zero-crossing controller in such a way that any subsequent signal from this sequence is analyzed only after some delay from its predecessor, i.e., the L2 signal would be analyzed after the L1D signal, L3 - after L2D, and L4 - after L3D. This is done to filter any noise on the input signal caused by jitter in the mechanical system.
The zero-crossing controller transforms the sequence of L1 .. L4 signals into control signals for all five counters as described above.
Counters 1 .. 4 determine if the input signal is linear on all intervals from L1 to L4 and to zero. If the input signal is linear (this is the case shown in Fig. 27), then the bad signal trigger is set to the good signal state to indicate that the zero-crossing point has been detected safely.
Counter 5 produces the zero-crossing pulse which, together with the output from the bad signal trigger, go to the direction detector to determine the direction in which the pulses from the V/F converter are counted in the signal integrator.
6.11 Direction Detector
The direction detector determines the direction in which the pulses from the V/F converter are counted by the signal integrator. Its block diagram is given in Figure 28.
The start signal from the system controller sets the direction trigger to the state defined by the state of the Pos/Neg signal which comes directly from the full wave rectifier.
After this, the direction trigger is toggled either by a change in the Pos/Neg line when the Bad Signal indicates that the zero-crossing point cannot be determined by the zero-crossing detector, or by the Zero-Crossing pulse in opposite case.
Fig. 28 Direction Detector. Block Diagram.
6.12 Signal Integrator
The Signal Integrator performs the following functions:
* it accepts V/F and encoder inputs and monitors them in up-down counters whose contents are placed in memory on commands from the trigger source;
* it processes encoder inputs in such a manner as to provide trigger signals only for absolute changes (increases or decreases) in the encoder position that coincide with a preferred direction;
* it selects sources of incoming V/F signals and trigger pulses;
* it pre-scales a number of trigger pulses by a given coefficient;
* for each period of the pre-scaled trigger pulses, it generates a stream of synchro pulses with given frequency and number of pulses;
* it uses synchro pulses to initiate subsequent readings of contents of all up-down counters and writes them into internal memory;
* it tests the functionality of its major components "on the fly" and informs the system controller if any error occurs;
* it contains a full 32-bit wide, dual access memory to hold data from all up-down counters and supports the system controller access to this data;
* it supports both accumulative and differential storage modes.
The Signal Integrator has the following technical specifications:
1) Number of trigger sources, total 8
* internal VXI TTL 1
* internal from Encoder 2
* external TTL 3
* external ECL 2
2) Resolution of the pre-scaler, bit 4
3) Maximum number of synchro pulses 255
4) Synchro pulse frequencies 0.125 Hz .. 250 KHz
5) Number of up-down counters 4
6) Counter size, bit
* Encoders 16
* V/F Converters 32
7) Memory organization
* type SRAM
* word size, bit 16
* number of segments 4
* number of blocks in a segment 4
* block size, word 8K
* overall volume, words 128K
8) Number of V/F signal sources 4
9) Number of encoder sources (external) 2
10) Monitored outputs TRIG_SOURCE, PRE_SCALER, SYNCHRO_PULSE
11) Interface DT9110, Register Based
12) Power supply External from VXI
The structure of the signal integrator is shown in Figure 29. Its detailed description is given in RD Controls Special Project Note 12.0.
One original part of the signal Integrator is an encoder filter. It allows elimination of false trigger pulses caused by encoder bouncing. An explaination of how the encoder filter works is given in Figure 30. This figure shows chosen models for both the encoder and the encoder filter, and the encoder filter timing diagram.
From the filter model, it is easy to see how the position counter will count only those up or down pulses that coincide with the preferred direction (direction line).
The scaler always monitors movement of the encoder. When the encoder is bouncing, the contents of the scaler is going both up and down.
The position counter is different. Its contents go only in one direction (up or down) determined by the preferred direction.
The comparator looks at contents of both the scaler and the position counter, and allows only those pulses that coincide with the preferred direction to be trigger pulses.
Fig. 29 Signal Integrator. Block Diagram.
Fig. 30 Encoder Filter. Models and Timing Diagram.
6.13 VXI Interface
This section is written by Al Legan for the SIM Module specification. It is adapted in this document because it describes the DT-9110 VXI-bus Register-Based Interface Card which is used in all in-house built VXI-bus modules.
The DT-9110 VXI-bus Register-Based Interface Card provides a complete VXI bus interface capable of performing all register based data transfers. It has a 4 row by 43 pin connector (see Table 9 below for pinout information).
Pin# Row A Row B Row D Row E Pin# Row A Row B Row D Row E
1 ---- ---- VD0 VD8 23 BVD4 BVD5 AM4 A15
2 ---- ---- VD1 VD9 24 BVD6 BVD7 A7 A14
3 ---- ---- VD2 VD10 25 BVD8 BVD9 A6 A13
4 ---- ---- VD3 VD11 26 BVD10 BVD11 A5 A12
5 ---- ---- VD4 VD12 27 BVD12 BVD13 A4 A11
6 ---- ---- VD5 VD13 28 BVD14 BVD15 A3 A10
7 ---- ---- VD6 VD14 29 INTRPT* ---- A2 A9
8 ---- ---- VD7 VD15 30 ---- ---- A1 A8
9 ---- INTL3 ---- ---- 31 ---- ---- IRQ1* IRQ2*
10 ---- INTL2 CLK SYSFAIL* 32 ---- ---- IRQ3* IRQ4*
11 ---- INTL1 AM0 ---- 33 ---- ---- IRQ5* IRQ6*
12 ---- ---- DS1* SYSRST* 34 ---- ---- IRQ7* ----
13 ---- MRST DS0* ---- 35 ---- ---- ---- ----
14 ---- ---- WRT* AM5 36 ---- RST REGRD* MODID
15 ---- ---- AM1 A23 37 ---- UASEL* A24 A25
16 ---- ---- DTACK* A22 38 ---- REGWR* A26 A27
17 ---- ---- AM2 A21 39 DDSEL* ---- A28 A29
18 ---- ---- AS* A20 40 LA0 LA1 A30 A31
19 ---- ---- AM3 A19 41 LA2 LA3 VCC VCC
20 ---- ---- IACK* A18 42 LA4 LA5 GND GND
21 BVD0 BVD1 IACKIN* A17 43 LA6 LA7 GND GND
22 BVD2 BVD3 IACKOUT* A16 ---- ---- ---- ---- ----
6.13.1 Register Description
The DT9110 incorporates all of the configuration registers required by the VXIbus specification, and decodes the address lines to provide a select signal (DDSEL*) for all A16 Device Dependent registers. All registers conform to the definitions and rules given in the VXIbus specification. The VXIbus register map is shown below.
DT9110 VXIbus DEVICE REGISTER MAP
Base Addr Register Name
3E DEVICE DEPENDENT
. .
. .
. .
08 DEVICE DEPENDENT
06 OFFSET
04 STATUS/CONTROL
02 DEVICE TYPE
00 ID/LOGICAL ADDRESS
The base address for the DT9110's device registers is determined by the device's unique logical address. The Logical address is determined by the value placed on the LA(7:0) pins, or is programmed by the system's Resource Manager if a value of FFH is placed on the LA(7:0) pins. The logical address corresponds to bits 6 -13 of the device register base address. Bits 14 and 15 of the base address are both 1. VXIbus accesses to the DT9110's registers are automatically detected and controlled by the DT9110. In order to achieve the greatest flexibility, the DT9110 implements only the configuration registers. If A16 Device Dependent registers are needed, (address 08 thru 3E ) they must be implemented external to the DT9110.
6.13.2 ID Register (Read Only)
BIT# 15<-14 13<-12 11<-0
CONTENTS DEVICE CLASS ADDRESS SPACE MANUFACTURER ID
DEVICE CLASS: This field indicates the classification of the DT9110 according to the following table. The default value is 11.
VALUE CLASS
00 Memory
01 Extended
10 Message Based
11 Register Based
ADDRESS SPACE: This field indicates the addressing mode(s) of the DT9110's operational registers according to the following table. The default value is 00.
VALUE MODE
00 A16 / A24
01 A16 / A32
10 RESERVED
11 A16 Only
6.13.3 Manufacturer ID
This number uniquely identifies the manufacturer of the device. The list of ID numbers is maintained by the VXIbus consortium. Each VXIbus device manufacturer has exactly one Manufacturer ID number. Numbers are assigned to manufacturers in decreasing order beginning with number 4095. See the VXIbus specifications for information on obtaining a manufacturer ID number. The default value is 0.
6.13.4 Logical Address Register (Write Only)
The Logical Address register is used to determine the DT9110's register base address. Each device in a system must have a unique Logical Address. The value of the DT9110's Logical Address is set by placing a value on the LA(7:0) pins. These pins contain internal pull-up resistors, allowing the use of a dip switch without the need for external resistors. If the value of FFhex is placed on the LA(7:0) pins, the DT9110 will become a dynamically configured (DC) device, meaning the value of its Logical Address register will be programmed automatically during initialization by the Resource Manager.
6.13.5 Device Type Register (Read Only)
The Device Type register is programmed by selectively cutting the jumper traces at locations RN1 and RN2 (See Fig. 4.9a, ID/DEVICE TYPE REGISTER CONFIGURATION). The Device Type register Fields are Defined by the VXIbus specification as follows.
BIT# 15 <- 12 11 <- 0
CONTENTS REQUIRED MEMORY MODEL CODE
REQUIRED MEMORY (Only required for A16/A24 and A16/A32 devices): These 4 bits contain a number m, which is between 0 and 15. The required memory usage is defined as
256a * 223-m,
where a is the value address space field in the ID register. This equation gives the amount of A24 VMEbus memory space (in bytes) resident on the device. The DT9110 will automatically decode the address bits to the corresponding resolution. The default value of this field is 0x0008, which corresponds to 32768 bytes (32 Kbytes) if the DT9110 is configured as an A16/A24 device, or 8388608 bytes ( 8 Mbytes) if the DT9110 is configured as an A16/A32 device. If the DT9110 is configured as an A16 only device, these four bits are the upper bits of the model code.
NOTE: If the DT9110 is configured as an A16/A24 device, the minimum size of the A24 memory is 256 bytes. The maximum size is 1/2 of the complete A24 VMEbus address space. If the DT9110 is configured as an A16/A32 device, the minimum size of the A32 memory is 65536 bytes (64 Kbytes). The maximum size is 1/2 of the complete A32 VMEbus address space. It is a good idea to limit the memory space of any one device to 1/4 of the available address space.
MODEL CODE: This field contains a unique card identifier which is defined by the manufacturer. In the case of an A16 only device, this field occupies all 16 bits of the Device type register. Model codes 0-255 (0-FFHEX) are reserved for Slot 0 devices. The default value for this field is 0. Therefore, if the device Type register value is not modified by the user, the system's Resource Manager may give a warning during initialization indicating "redundant Slot 0 capability", or other similar warning. Programming a model code value greater than 255 will eliminate this warning.
6.13.6 Status Register (Read Only)
BIT# 15 14 13<-4 3 2 1 0
CONTENTS A24/A23ACTIVE MODID* NOTUSED READY PASSED SYSFAILINHIBIT RESET
A read of this register provides information about the DT9110's status according to the following bit definitions.
A24/A32 ACTIVE: This bit is only valid for A16/A24 and A16/A32 devices. A one (1) in this field indicates that the DT9110's A24 or A32 registers can be accessed. This bit reflects the state of the Control registers A24/A32 ENABLE bit.
MODID*: This bit reflects the inverted state of the MODID pin.
READY: This bit is used to indicate to the system controller that the DT9110 is ready to begin normal operation. This bit is cleared to 0 during reset conditions and automatically set to 1 when the device is ready for operation.
PASSED: The PASSED bit is normally used to indicate the success or failure of a device's self test. Because the DT9110 does not execute a self test, this bit is automatically set to 1 when the READY bit is set to 1.
SYSFAIL INHIBIT: This bit reflects the state of the SYSFAIL INHIBIT bit of the control register.
RESET: This bit reflects the state of the RESET bit of the control register.
6.13.7 Control Register (Write Only)
BIT# 15 14 13<-4 3 2 1 0
CONTENTS A24/A23ACTIVE MODID* NOTUSED READY PASSED SYSFAILINHIBIT RESET
A write to this register causes specific actions to be executed by the DT9110. These actions are described below.
A24/A32 ENABLE: A one (1) in the field enables access to the device's A24 or A32 VMEbus registers. A zero (0) disables such access.
SYSFAIL INHIBIT: A one (1) in this field disables the device from driving the SYSFAIL* line.
RESET: A one (1) in this field forces the device into a soft reset state.
6.13.8 Offset Register (Read/Write)
This register is used only for A16/A24 and A16/A32 devices. This 16-bit register defines the base address of the device's A24 or A32 VMEbus register. The m+1 most significant bits of the Offset register are the values of m+1 most significant bits of the device's A24 or A32 register addresses, where m is the value of the Required Memory field of the DT9110's Device Type Register. The 15-m least significant bits of the Offset register are meaningless. The DT9110 automatically maps the Offset register bits 15 -> 15-m to the address lines A23 -> A23-m for A24 registers, or to lines A31 -> A31-m for A32 registers. When a VXIbus access to the device's A24 or A32 registers is detected, the DT9110 asserts the UASEL* (upper address select) signal, which can be used as a device select. The Offset register is always reset to 0 by
a reset or power up condition.
6.13.9 ID/Device Type Register Configuration
The ID register and Device Type register can be custom configured by selectively cutting configuration traces provided for this purpose, or adding jumpers to override traces that have already been cut. The locations of the configuration traces are shown below.
Fig. 31 ID/DEVICE Type Register Configuration.
The default values for the ID register and Device Type register are as follows.
6.13.10 ID Register
BIT# 15 <- 14 13 <- 12 11 <- 0
BINARY VALUE 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DEFINITION DEVICE CLASS (register base) ADD. SPACE = A16/A24 MANUF. ID = 0
6.13.11 Device Type Register
BIT# 15 <- 12 11 <- 0
BINARY VALUE 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DEFINITION REQUIRED MEMORY32768 bytes (A24 register)or 8388608 bytes (A32 registers) MODEL CODE = 0
To change a bit from a '0' to a '1', the configuration trace corresponding to the bit must be cut. To change a bit from a '1' to a '0' (which implies that the configuration trace has already been cut), a jumper wire must be installed between the two pin holes normally connected by the trace. To configure the registers with dip switches, simply cut all configuration traces and install a 8-position DIP switches in locations SW1, SW2, SW3, and SW4 (see Figure 4.9a).
6.13.12 A16 Device Dependent Register Implementation
The VXI Device Dependent registers, which are located at address 08-3F relative to the DT9110's VXIbus base address, are intended to be implemented external to the DT9110. The buffered VXI data bus pins (BVD15-BVD0) are provided as the data path between the VXI data bus and the A16 Device dependent registers. Enable and direction control for the "on board" VXI data buffers is provided automatically by the DT9110.
The DT9110 provides special signals to control access to the external register locations. These external register control signals consist of a device select signal, DDSEL*, and independent read/write control lines, REGRD*, REGWR*. The control signal DDSEL* is asserted whenever the VXIbus accesses an A16 Device Dependent register location. The VXIbus address lines from the back plane, A5-A1, can then be used to decode the individual registers. A block diagram showing the implementation of the A16 Device Dependent registers is given in Figure 4.12a.
Fig. 32 Implementation of the A16 Dependent Registers
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