Special Project Note 12.1
Precision Automatic Flux Measurement System (PAFMS)
Signal Integrator & Memory Module (SIM)
March 13, 1996
Table of Contents
1. General Description 2
2. Technical Characteristics 3
3. PAFMS Signal Integrator Structural Overview 6
3.1 Elements of the module 7
3.2 Defined Buses 7
3.3 Operational Summery 9
Figure 1. Precision Automatic Flux Measurement System (PAFMS)
1. General Description
The PAFMS SIM module is designed to occupy one single wide C-size VXI module. This module will have the capability of being controlled either directly by an embedded processor, or indirectly with a VXI Slot-Ø dumb controller. All external communication from a host computer to the PAFMS SIM module is via an GPIB interface to the controller. Figure 1 shows the typical environment in which the PAFMS SIM module will be working in.
The PAFMS SIM module performs the following tasks in the systems shown in Figure 1:
* It monitors the V/F and position encoder inputs using Up-Down counters. The outputs from the counters are placed in memory on command from the trigger source.
* It processes encoder inputs in such a manner as to provide trigger signals only for absolute changes in encoder position that coincide with a preferred direction.
* It selects external sources of incoming V/F signals and positive or negative edge trigger pulses.
* It performs a pre-scale on a number of trigger pulses by a given coefficient.
* Within each period of the pre-scaled trigger pulses, it generates a stream of synchro pulses with a given frequency and number of pulses.
* It selects Synchro pulse output mode; one pulse for each pre-scale pulse; or multiple pulses for each pre-scale pulse.
* Synchro pulses are used to initiate subsequent readings of contents of all Up-Down counters and writing them into internal memory.
* It test the functionality of its major components "on the fly" and informs the host computer system if an error occurs.
* It contains a full 32 bits wide dual access memory, to hold the contents of the counters and at the same time to provide the host computer with access to this data. The host computer controls all memory arbitration associated with the dual access memory.
* It supports both accumulative and differential storage modes.
2. Technical Characteristics
1) Trigger sources:
* Edge trigging * or * Software selectable
* internal VXI TTL 1
* internal from Encoder 2
* external TTL 3
* external ECL 2
* Maximum input frequency 250 KHz
* Minimum input pulse width 200 ns
2) Resolution of the pre-scaler 2n; n = 4 bits
3) Maximum number of synchro pulses 255
4) Synchro pulse frequencies 0.125 Hz...250 Khz
(see synchro pulse frequency table 10.2B)
5) Number of up-down counters 4
6) Counter size
* Encoders 32 bits
* V/F converters 32 bits
7) Memory organization:
* type: SRAM
* word size 32 bits
* number of segments 4
* number of blocks in a segment 4
* segment size 8K bytes
* block size 32K bytes
* overall volume 512K bytes
8) Number of V/F signal sources 4
9) Number of monitored V/F signal sources 2
10) Number of encoder sources (external) 2
11) V/F and encoder inputs:
* V/F SIGØ
* Quadrature Encoder inputs Ø-5 Volt TTL
12) Monitored outputs TRIG_SOURCE
* Internal User's Parallel Interface
* External DT9110's Register Based VXI
14) power supply External (from VXI)
15) Embedded microprocessor None
16) Hardware self-test features Checking for memory boundaries,
Checking data written into memory.
17) Data storage modes Accumulative
Figure 3. Signal Integrator and Memory Block Diagram
3.PAFMS Signal Integrator Structural Overview
The PAFMS SIM module's design objective is to accept as input, quadrature encoder signals (phase related pulses and reference), V/F signals (pulse stream and direction), triggering signals (TTL and ECL type pulses), and VXI interface signals (coming from the VXI Daughter-card by Interface Technology). The SIM module will at predetermined intervals (user definable) count V/F pulse streams and store them into on board memory (Measure Mode). All on board memory and I/O devices are accessible to the host computer only during idle time (Idle Mode).
The block diagram in Figure 3 outlines the basic structure of the SIM module. The module is divided into six main components, interface circuitry, trigger source circuitry, counter circuitry, status controller circuitry, memory controlling circuitry, and host I/O controller circuitry.
The Interface circuitry contains three main components, encoder circuitry, trigger source circuitry, and V/F input circuitry. The encoder circuitry is divided into two sub-circuitry's, encoder noise pulse filtering circuit and encoder reference interface. The encoder noise pulse filtering circuit is designed to validate input logic levels and eliminate encoder dither. Encoder reference signals are pre-conditioned using a schmitt action input buffer to drive the encoder counter circuitry. The trigger source circuitry is divided into three sources, TTL, ECL, and VXI. The TTL signals are pre-conditioned using a schmitt action input buffer to drive the trigger source multiplexer. The ECL input signals are connected to an ECL-to-TTL converter which is then routed to the trigger source multiplexer. The VXI signal is a TTL level pulse derived from the VXI backplane pin number A23. This signal is then routed to the trigger source multiplexer. The V/F input circuitry, pre-conditions the signals using a schmit action input buffer to drive the input s into the V/F counter multiplexer.
The Trigger Source circuitry chooses the incoming trigger source pulses, pre-scales them with a programmable coefficient, and generates the output stream of synchro pulses, at the pre-programmed frequency and with the pre-programmed pulse number.
The Counter circuitry contains two main components, Encoder Counters, and V/F Counters. The Encoder Counter circuit accepts as input a quadrature encoder pulse streams. The circuit monitors the phase relationship of the encoder two pulse streams and only counts pulses in the preferred direction. The V/F counter circuit accepts an input pulse stream from one of the four V/F sources. Contents of both Encoder and V/F Counters are written into memory at each synchro pulse.
The Status Controllers main purpose is to monitor the SIM module's functionality "on the fly". It checks memory boundaries, validity of data written into memory, and presence of synchro pulses during measurement periods.
The Memory Controlling circuitry is divided into three main components, Internal, Test, and Host Memory Controller. The Internal Memory Controller is a finite state machine. The cycle of the state machine begins at each synchro pulse produced by the Trigger Source Controller. The action of the state machine is to write into memory contents of the Encoder and V/F Counters. The Test Memory Controller will test the validity of the memory by writing and reading data in each memory cell. This process is performed at boot-up or at user command (mode Test). The Host Memory Controller allows the host computer to directly access all SIM memory via the VXIbus Slot-Ø controller. Memory access by the host computer is only allowed while in Idle Mode.
The Host I/O Controller allows the host computer to access all SIM I/O registers and performs "cold or warm" resets on the module.
All VXIbus communication to and from the SIM module is via the VXI Daughter-card DT-9110 from Interface Technology .
The six main components as described earlier are implemented using FPGA's technology whenever possible.
3.1 Elements of the module
The SIM Module includes the following elements as outlined in block diagram Figured 3:
* Encoder Interfaces;
* Trigger Source Interface;
* V/F Interface;
* VXI Interface;
* Trigger Source Controller;
* Two Encoder Up-Down Counters;
* Two V/F Up-Down Counters;
* Internal Memory Controller;
* Test Memory Controller;
* Host Memory Controller;
* Status Controller;
* I/O Controller;
* Hardware Reset (manual and remote);
* Memory (128K * 32-bit words CYM-1836PJ-30C).
3.2 Defined Buses
The SIM Module design includes a number of control, data, I/O, and memory signals. These signals are grouped into individual buses. The following outlines the names of the buses:
* Control Bus;
* Data Bus;
* I/O Bus;
* Memory Bus.
The individual signal names associated with the buses are as follows.
* ENCENAØ -- Encoder Ø counter enable;
* ENCENA1 -- Encoder 1 counter enable;
* VF_ENAØ -- Voltage to frequency Ø counter enable;
* VF_ENA1 -- Voltage to frequency 1 counter enable;
* FILTENAØ -- Filter for encoder Ø enable;
* FILTENA1 -- Filter for encoder 1 enable;
* V_FSIGSØ -- Signal selection Ø (VF source);
* V_FSIGS1 -- Signal selection 1 (VF source);
* ENCTRGØ -- Encoder trigger pulse Ø;
* ENCTRG1 -- Encoder trigger pulse 1;
* REFØ -- Encoder reference reset Ø;
* REF1 -- Encoder reference reset 1.
* D00...D31 -- 32 bit data lines.
* ENCRDØ -- Read encoder counter Ø;
* ENCLDØ -- Load encoder counter Ø;
* ENCRD1 -- Read encoder counter 1;
* ENCLD1 -- Load encoder counter 1;
* FILTRDØ -- Read filter for encoder Ø;
* FILTRDØ -- Read filter for encoder 1;
* REFRD -- Read reference source;
* REFLD -- Write reference source;
* VFRDØ -- Read V/F counter Ø - 32 bits;
* VFLDØ -- Load V/F counter Ø - 32 bits;
* VFRD1 -- Read V/F counter 1 - 32 bits;
* VFLDL1 -- Load V/F counter 1 - 32 bits;
* SOURCRD -- Read trigger pulse source;
* SOURCLD -- Load trigger pulse source;
* SYNCHRD -- Read synchro pulse generator;
* SEGRD -- Read segment;
* SEGLD -- Load segment;
* MODERD -- Read mode;
* MODEWR -- Write mode;
* IMCADRD -- Read internal memory controller address;
* TADDRD -- Read test controller memory address;
* TSEGRD -- Read test controller segment address;
* SOFTREF -- Software Reference signal;
* MEMAD00 -- 32 bit Memory addressing
to Bits Ø through 31
* /RMCE1_2 -- Memory segment 1 & 2 select lines
* /RMCE3_4 -- Memory segment 3 & 4 select lines
* /RAMWE -- Memory Write enable
* /RAMOE -- Memory Read enable
* /ENCOEØ -- Encoder counter Ø output enable
* /ENCOE1 -- Encoder counter 1 output enable
* /VFOEØ -- V/F counter Ø output enable
* /VFOE1 -- V/F counter 1 output enable
3.3 Operational Summery
The SIM Module has three modes of operation. They are Idle, Measurement, and Test. During Idle mode the external host computer will configure the module's trigger source, triggering edge positive or negative, pre-scalar frequency, number of synchro pluses per trigger pulse, and V/F source. When a trigger source produces a synchro-pulse, the internal memory controller executes four sequential iterations consisting of read, write, read and compare operations. The period of each iteration is chosen to satisfy the requirement of having a maximum synchro-pulse frequency of 250 KHz. During each iteration, data from all encoders and V/F counters are written into memory.
During each iteration the status controller is checking data validity, memory boundary violations, counters overflows, and presence of synchro-pulses during the measurement mode. If any one of them fails to operate normally, the module pulls the VXI interrupt line, informing the host computer of the error condition.
When the SIM module is placed in Test mode, the module will perform a on board diagnostic sequence. This diagnostic process includes checking data validity, memory boundary violations, counters overflows, and presence of synchro-pulses during the measurement mode. If any one of them fails to operate normally, the module pulls the VXI interrupt line, informing the host computer of the error condition.
The host computer reads from or writes into I/O registers via the host I/O controller. This process can be performed within measurement mode, but it is inhibited if the SIM is writing to memory at the same time. The host computer has unrestricted access during the Idle mode. All commands from the VXIbus are processed by the on board VXI Daughter-card DT-9110 by Interface Technology.
On every power up cycle, the SIM goes through a reset state which zeroes out all I/O registers, encoder counters and V/F counters. The reset process can be initiated either manually by the front panel reset button or remotely via the VXI interface (software reset).