RD Controls Hardware Release Note 26.0
CAMAC C1151 Module
Power Supply and Ramp Controller
R. West, W. R. Knopf, M. Kuplic
January 24, 1991
Introduction
The C1151 module is a single width CAMAC module which provides a precision
reference voltage, control signals, and status readbacks for external
devices such as power supplies.
Ramp generation is accomplished by periodic updates of the on-board
D/A converter by a module-resident microprocessor executing
specific software routines. Access to the module is through
standard CAMAC functions across the dataway or via one of two serial ports.
The serial interface consists of an RS232 port on the front panel
accessible through a four-pin LEMO connector and a port on the Viking connector
which can be hardware-configured as RS232 or RS485, thus allowing data rates
of up to one megabits per second.
CAMAC functions use a 16-bit wide data path (R1-R16, W1-W16) on the
dataway to transfer data to and from the module.
All interface signals to external devices are available on a standard
CAMAC 36 pin Viking I/O connector at the rear of the module. See Appendix
C for pin connections.
Hardware Description
All peripheral devices are controlled by a 16-bit general purpose
microprocessor (Zilog Z8002) at a 10 MHz clock rate. Memory support consists
of jumper selectable 16/64 kbyte of EPROM and 16/64 kbyte of static RAM.
A 2K x 8 bytewide non-volatile RAM provides storage of parameters for
power-up conditions. Timer interrupts, bitsize I/O ports, and vector
generation for other interrupt sources are supported by a Peripheral
Controller (Zilog Z8036 CIO). See Appendix A for memory and peripheral devices
address mapping.
The reference voltage is generated by a 16-bit D/A converter
(BB-DAC703), buffered to the I/O connector through a voltage follower buffer
amplifier (PMI BUF-03).
As an option, analog signals can be read back through a 12-bit, left
justified A/D converter (AD574). The signal to the A/D is buffered through
an input op-amp (BB-INA117).
Four control outputs are isolated through the use of reed relays
(Gordos 831C-1). These provide for the power supply control functions
ON, OFF, RESET, and POLARITY.
Eight sense input bits for status read are TTL inputs with 220 Ohm
pull-up resistors.
Tevatron Clock decoding circuitry allows for interrupt generation by
software selectable clock events. A 256 x 1 mask memory allows for
enabling or disabling of events by writing a `1' or `0', respectively, to
the corresponding location. All unmasked events are buffered through
a 64 x 8 FIFO to prevent loss of events due to processor latency.
Note that the module accepts the Tevatron Clock as decoded clock and
data signals on dataway lines P1 and P2, respectively, thus requiring
the presence of the new version of the Crate Controller. If not used,
jumper J5 should be removed and jumper J4 set to the pull-up position.
The CAMAC dataway interface consists of two 16-bit data latches, one
each for read and write functions.
All valid functions requiring processor intervention generate vectored
interrupts with a unique vector provided for each function.
See Appendix B for interrupt vector assignments.
To ensure software execution integrity, a hardware heartbeat/reset feature
is provided. Bit number one of port B (Z8036) must be toggled at a
periodic rate to generate an edge which retriggers a time-out counter in the
micromonitor I.C. (Dallas DS1232). Upon timing out, this chip asserts the
hardware reset line.
Note: When using an in-circuit emulator to single step this module,
the retrigger signal has to be moved via a jumper to the `MEMREQ' signal
to prevent the occurrence of continuous resets.
CAMAC Hardware Interface
- Field programmable decoder PROM
- Inputs = CAMAC /N, /F1 - /F16, /A1 - /A16
- Outputs = /X, function lines /CF0 - /CF6
- An X response is generated for all valid functions and subaddresses.
- Allows 64 read functions, 48 write functions, and
15 control functions (including F8A0 and F9A0)
- Function codes and sub-addresses can be assigned in any
combination as long as they follow the following format:
- 0XXXXXX = Read Functions
- 10XXXXX = Write Functions
- 110XXXX = Write Functions
- 111XXXX = Control Functions, with the exception of
- 1111111 = Illegal
- 1111110 = Pre-assigned to F8A0 - Test LAM
- 1111101 = Pre-assigned to F9A0 - Hardware Reset
- EPM5032 Altera Max-EPLD programmable logic chip
- Inputs
- /CF0 - /CF6 from Decoder PROM
- /CMCRD, /CMCWR - decoded CPU access signals for CAMAC read/write.
- LAM - from CIO, indicating LAM present.
- /S2 from CAMAC Dataway.
- /INTACK - Vectored Interrupt Acknowledge from Interrupt arbitration logic.
- /Z - Initialize from CAMAC Dataway
- Outputs
- /RESET - CAMAC Initialize or F9A0
- D0 - D6, Function code latch and comparator; tri-stated outputs enabled
by /INTACK.
- /Q - Q-response (buffered) to CAMAC Dataway.
- /CINT - Interrupt Request to interrupt logic.
- /WBSTB - Strobe for CAMAC Write Data buffer.
- Interrupt and Q-response generation - All CAMAC requests are ignored and
no Q is generated if at the
beginning of the dataway cycle a CAMAC interrupt is still pending
(/CINT = TRUE) or
/INTACK is active. Exceptions are TEST LAM and RESET, which are
processor independent.
Logic Generation
Read Functions
- /CINT is generated on every read cycle except for a read cycle returning
a /Q = TRUE.
- /READFF is set to TRUE (low) by a microprocessor write to the CAMAC
read buffers
- /Q = TRUE if a read function is the same as the previous CAMAC function
and /READFF = TRUE.
- /READFF is set to FALSE at the end of every valid CAMAC cycle.
Write Functions
- /Q = TRUE if /WRTFF = TRUE (low) and /CINT = FALSE.
- Data is strobed into the write buffers at S2 time only if
/Q = TRUE.
- /WRTFF is set to FALSE at the end of the CAMAC write cycle into the write
buffers
- /CINT is generated only if /Q = TRUE.
- /WRTFF is set to TRUE by a microprocessor read of the CAMAC write buffers
Control Functions
- /Q = TRUE if /CINT = FALSE.
- /CINT is generated only if /CINT = FALSE.
- /INTACK will reset /CINT to FALSE.
Special Functions
- Test LAM (F8A0)
- No /CINT is generated.
- /Q = TRUE if LAM = TRUE.
- Reset Module (F9A0)
- No /CINT is generated.
- /Q = TRUE.
- A hardware reset is generated (250 msec).
Ramp Generation
- The first version of the firmware emulates the C150 module as closely as
possible.
- Level
- C150 : 0 to 10.240 Volts, 14 bits, value of LSB is 0.6250 mV.
- C1151: 0 to 10.000 Volts, 15 bits, value of LSB is 0.3052 mV.
- Slope
- C150 : 0 to 100 Volts/sec., 11 bits, value of LSB is 48.83 mV/sec.
- C1151: 0 to 100 Volts/sec., 11 bits, value of LSB is 48.83 mV/sec.
- All level and slope values are saved in non-volatile RAM from which
they are restored upon power-up.
- Memory resident values for each segment are:
- DAC delta(v) to be applied to the output every millisecond.
This is a 32-bit value (increment + remainder).
- Update counter which is decremented every millisecond. All DAC updates
stop when this counter reaches zero.
- Clock Interrupt Routines
- Load Delta(v) and Update counter for the appropriate segment
- Read from non-volatile RAM into static RAM.
- The values used by the 1 KHz ramp update routine are:
- Delta(v) = (slope * 100) / 16.
- Update counter = (segment level - present level) / delta(v).
Diagnostics
Diagnostic commands may be directly input to the module by connecting a
computer terminal to the front panel RS232 port. A HELP menu displays the
commands which are available to assist in trouble shooting. The following
commands can be executed at a terminal:
- GO m - Execute program at location m
- HE n - Display Help menu n
- HL - Hex Load (Intel format)
- DB/DW/DL m n - Display bytes/words/longwords from m to n
- DR - Display Register contents
- IB/IW m - Input Byte/Word from I/O location m
- OB/OW m - Output Byte/Word to I/O location m
- MB/MW/ML m - Modify byte/word/longword at location m
- MR n - Modify Register n
- WM m d - Write Memory with data d at location m
- CK - Display TCLK events
- CE/CD - Enable/Disable CAMAC interrupts
- LE/LD - Enable/Disable LAM
- RE/RD - Enable/Disable RAMP mode
- SW - Display/Modify Switch settings
- TD - Time-of-Day Display/Modify
- ST - Display module status
- DA - Set DAC value
- LB - List breakpoints
- RB - Remove breakpoint
- SB - Set breakpoint
Status LEDs
- ST H - Ramp enabled
- ST A - C = Phase number
Status Word
- low byte = Viking Connector status input lines
- bit 00 - REMOTE_LOCAL: REMOTE if 0, LOCAL if 1
- bit 01 - TRIP: OKAY if 0, TRIP if 1
- bit 02 - ON_OFF: ON if 0, OFF if 1
- bit 04 - REVERSE: REVERSE if 0, NORMAL if 1
- bit 05 - REVERSE_REMOTE: REVREM if 0, REVLOC if 1
- high byte = module status
- bit 09 - RAMP_DC: DC if 0, RAMP if 1
- bit 10 - NO_CLOCK: CLK_OK if 0, NO_CLK if 1
- bit 11 - LAM: enabled if 1
- bit 12 - Polarity setting: polarity normal (contacts open) if 0,
polarity reverse (contacts closed) if 1
Switch Settings
APPENDIX A
ADDRESS ASSIGNMENTS
Memory space shown in 16 kbyte EPROM, 16 kbyte RAM configuration
15------------------------------0
0000 - | |
| |
| Code Segment in |
| EPROM |
| |
7FFF - | |
|-------------------------------|
8000 - | PSAREA |
|-------------------------------|
8300 - | |
| RAM |
| |
| |
FFFF - | SYSTEM STACK |
---------------------------------
I/O Space - All 8 bit I/O devices are located at an odd byte address
15--------------7---------------0
0000 - | | |
| | Z8036 CIO |
00FF | | |
|-------------------------------|
0100 - | | |
| | 2692 DUART |
01FF | | |
|-------------------------------|
0200 - | | TCLK |
| | Mask RAM |
03FF - | | |
|-------------------------------|
0400 - | | TCLK FIFO |
|-------------------------------|
0480 - | | F.P. LEDs |
|-------------------------------|
0500 - | DAC703 (D/A) | D/A data write
|-------------------------------|
0580 - | AD574 (A/D) Convert | I/O write to start conversion
0582 - | Data | A/D data read
|-------------------------------|
0600 - | CAMAC Buffers |
|-------------------------------|
0680 - | | ON Relay |
0682 - | | OFF Relay |
0684 - | | RESET Relay |
0686 - | |POLARITY Relay |
0688 | | Viking I/O | I/O status read
|-------------------------------|
1000 - | | |
| | NV RAM |
1FFF - | | |
---------------------------------
APPENDIX B
INTERRUPT VECTOR ASSIGNMENTS
APPENDIX C
VIKING CONNECTOR SIGNAL ASSIGNMENTS
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