EPICURE Design Note 106.0


System Hardware Design Overview

Mark Kozlovsky

Therese Watts

Brian Kramper

Walter Knopf

Terry O'Brien

Terry Kiper

Al Legan

Al Forni

September 23, 1991

1. Foreword

Historically, the Accelerator Division (AD) and the Research Division (RD) shared the same clock system, namely Phase Clock (Experimental Clock). Eventually, AD upgraded their clock system to what is now known as the TEV (Tevatron) Clock, but at that time the RD did not follow suit.

While the decision of upgrading the Beamline Clock System to the TEV Clock was made by the RD/Controls Group quite some time ago, visible contours of progress and a plan of how to fully achieve this goal start to be evident only now. These plans are finalized in this document.

This paper represents the culmination of discussions within the Clock System Design Group that took place over the last couple of months. A number of meetings were held to educate group personnel on the existing Phase and TEV clock systems, to identify deficiencies of these systems, and to plan a migration path towards the complete transformation of the Phase clock system to the TEV clock, in order to support a single Clock System throughout the entire Fermilab areas.

While it is a pleasure to acknowledge and thank everybody in the design team for their valuable contributions, a special recognition is attributed to the Design Group Leader, Walter Knopf, whose effective leadership and eagerness to share his vast knowledge of the existing systems with all of us made our meetings most productive and decisive.

2. Disadvantages of the existing Clock Systems

a) The existing Beamline Clock System has been designed to decode only 15 clock events from an overall 256 events available after full TEV Clock decoding.

The original EPICURE System design always assumed the TEV clock as its main timing source, but complete conversion was postponed due to lack of funding.

While the present Beamline Phase Clock is adequate for the current mode of operation, it will not be sufficient to run during the main injector era when interspersed cycle types are anticipated.

Thus, it will be necessary to decode all events in order to recognize the cycle type.

b) There is a major difference between the AD and the RD in the way they broadcast their basic timing signals: the AD uses TEV Clock, the RD - Phase-Reversal Clock, which is derived from the TEV Clock.

This makes module exchange between the two divisions impossible. This also creates confusion among the users who are forced to understand two different clock systems. Our goal is to support one lab wide clock system.

c) The RD is dependent on clock assignments made by the AD.

All Clock assignments made by the AD are global and cover all systems within the laboratory, i.e. Linac, Booster, 8Gev, Main Ring, Tevatron, Switchyard, EAD, etc. This has led to the assignment of most of the 254 available events, with only of a few of them left for future use in the Beam Lines.

Our new Clock Generator Module would allow us to suppress events which are of no interest to the EAD and re-use these event numbers for timing events of our own choosing.

d) The TEV Clock hardware has features that are relatively difficult to support.

Without going very deeply into discussion of technicalities, we refer only to such features, as

* dealing with distortions in transmission lines;

* using fixed thresholds for clock restoration;

* employing one shots for event decoding;

* the necessity of individual tuning of TEV clock repeaters.

Our clock design takes these factors into consideration and attempts to solve them by using state of the art circuitry in conjunction with 10 Mhz baseband transmission (the AD uses 48 Mhz carrier to transmit 10 Mhz clock signal).

e) The existing Phase Clock is incompatible with the RD CAMAC Crate and Power Supply Controllers' clock decoding schemes.

The aforementioned modules have already employed the TEV clock as their basic timing signal in anticipation of the Phase to TEV conversion.

As this is in contrast with all our old modules, which use the Phase-Reversal clock, we need to continue replacement of these old modules.

3. Prime Objectives of the Clock System Upgrade

Our prime objectives are:

* Using one global Clock System across both the Accelerator and Research Divisions

* Getting a more flexible Clock System for the Beamline Experimental Area

* Increasing system resolution

* Increasing system reliability

* Providing backward compatibility with the old Clock System in order to make possible use of some old modules.

These objectives will be achieved through:

* Adherence to the AD's existing decoding scheme

* Improvements in clock generation

* Use of smart modules each providing full module's programmability

* Use of state-of-the-art communication links and up-to-date hardware drivers

* Continuing support of the phase-reversal clock.

4. Signal Platforms

At this time, two primary clock signals are simultaneously broadcasted around Fermilab: TEV and Phase-Reversal Clocks. They represent two different approaches to a single problem: how to transmit a clock signal over long distances reliably.

The AD has adopted the TEV Clock, but the RD still uses the Phase-Reversal Clock. Both of these platforms have their pros and cons that were fully discussed during the meetings.

We agreed that, in order to have one common platform for a clock system across both divisions, we should employ the AD's TEV Clock with their Modified Manchester Encoding Scheme, but without RF modulation.

At the same time, we must also continue to support the Phase-Reversal Clock for those old modules that utilize it, until all of them can be replaced with new modules built around the TEV Clock.

Figure 1 shows some properties of the TEV Clock and also indicates potential problems one can face when dealing with it. Among them are a need for signal restoration and possible error occurrence in output codes caused by distortions in the broadcasted signal. These distortions can be introduced into the signal by long transmission lines or by differences in their terminations. Another weak point one should watch out for is the stability of the decoding pulse. If unstable, it can cause decoding errors.

The list of CAMAC modules that decode TEV Clock and are supported by the RD/Controls Group includes:

* C1150 - Beam Structure Monitor (not commissioned)

* C1151 - Power Supply Controller

* C1045 - Motor Controller

* C1032 - SWIC Controller (not commissioned)

* C1010 - MADC Controller (not commissioned)

* C1091 - High Resolution Timing Module (exists in prototype).

Figure 2 illustrates the phase-reversal clock encoding scheme and some of the signal properties.

Usually the Phase-Reversal Clock is transmitted constantly as a sequence of 0-cycles. When there is a need to deliver an event number, then a sequence of 1-cycles is produced in which the number of cycles directly corresponds to the event number.

The list of CAMAC modules that decode the Phase-Reversal Clock and are supported by the RD/Controls Group includes:

* 090 - 12-Output Clock Fan Out

* 091 - 8-Channel Timer with Reference Selectable

* 093/096 - 3-Output Clock Repeater with Four T-Events at Front Panel

* 128 - Phase Clock Repeater

* 150 - Ramping Power Supply Controller (almost obsolete)

* 179 - Phase-Reversal Clock Generator

* 200 - TEV to Phase Clock Generator

* Unknown - Radiation Safety Interlock Chassis

5. Clock System Architecture

Three new modules will be designed to build the new Clock System. They are:

* C1200 - Tevatron Clock Generator

* G128 - Tevatron Clock Repeater/Fan Out

* G200 - Tevatron to Phase Converter.

Preliminary specifications of the modules are given in the appendix to this document. The appendix is also supplemented with a research paper on state-of-the-art transmission lines and up-to-date drivers for TEV Clock broadcasting.

People currently assigned to different projects involved in this upgrade are:

* Clock System Design Overview - M. Kozlovsky

* Clock Support Software:

a) C1200 Support Application - unknown

b) C1200 Frontend Handler - K. Dabous

c) VME Timer Support - D. Kline

d) Clock Event Display Application - unknown

* C1200 - W. Knopf

a) Hardware

b) Embedded Software

* C1091

a) Hardware - A. Legan

b) Embedded Software - K. Dabous

* G128 - A.Forni

* G200 - T. O'Brien

* Research on lines and drivers - T. Kiper

The preliminary time estimation for each of these projects is given in Table 1. It includes time figures for:

* hardware - hardware and embedded software design, prototyping, debugging, and testing

* application software - development, debugging, and testing.

The estimation does not include time needed for system fabrication, installation, and maintenance.

Table 1.

No. PROJECTS TIME (man-months)

1 C1200 6

2 C1091 6

3 G128 4

4 G200 4

5 Research on links and drivers 3

6 Clock System Design Overview 1

7 C1200 Support Application 9

8 C1200 Frontend Handler 2

9 VME Timer Support 3

10 Clock Event Display Application 3

Total: 41

The actual time schedule for the different design phases will be set after the project's approval.

A System Architecture is given in Figure 3. The TEV Clock Generator C1200 will be placed into a crate, which is a part of the Beamline System. Ideally this crate would be at the Experimental Area's Operations Center (OPs Center).

C1200 will receive its incoming TEV Clock signal from NS1 which will be connected via an fiberoptic link with the X-Gallery. The fiberoptic cable from the X-Gallery to NS1 is anticipated to go in during the summer of 1992.

During this upgrade, we would like to have one more fiberoptic cable installed between NS1 and the Ops Center. This fiberoptic link would drastically improve signal transmission between the two areas by eliminating length problems. The present coax cable exceeds the maximum length of the link specified for the TEV Clock Repeater/Fan Out.

While it is not mandatory for the C1200 to be in the Ops Center, it is most desirable in order to solve the aforementioned length problems and also because it would allow us to continue using the existing cables for clock signal distribution. Changing the distribution point will result in additional cabling costs not accounted for in this proposal.

A clock signal from the C1200 will be transmitted to every service building where it will again be restored and converted, if necessary, to the phase-reversal clock signal. Both TEV and Phase-Reversal Clock signals will then be sent to CAMAC crates where they are then used as reference signals for process synchronization.

6. Upgrade Cost Estimation

An upgrade cost estimation is given in Table 2.

Table 2.


Module Name Estimated Cost per Unit System Requirements Total Unit Cost

C1200 $1,200 5 $6,000

C1091 $800 50 $40,000

TEV Clock Repeater $200 50 $10,000

TEV to Phase Clock Converter $200 25 $5,000

Fiberoptic Link from NS1 to Ops Center 1 $40,000

Miscellaneous $4,000

Total Hardware Cost: $105,000

Contingency $25,000

Total Upgrade Cost: $130,000

The contingency was calculated as approximately 25% of the total hardware cost.

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