Controls Hardware Strategic Plan

March 13, 1996

"Without a vision, the people perish."
King Solomon - Proverbs

Introduction:

In an era of staffing caps and budget cuts it is essential that we become more efficient in using the resources available. In order to accomplish this and also keep up with the incredibly fast pace of technology, the engineering groups in the Controls Department have developed this strategic plan which we will use to guide us in our individual engineering decisions.

We recognize that one of the most satisfying aspects of engineering is exercising creativity in designs. We also recognize that a small efficient group cannot simultaneously support all possible platforms, processors, buses etc. Creativity can exist with guidelines! We will strive wherever practical to build on existing systems and software while moving ahead toward our vision of the future.

This document is a working attempt to formalize that vision as well as to develop a list of strategic priorities which must be addressed if we are to build momentum toward the future. The policies presented here are intended to help guide the work of each member of the Controls Department. A yearly review and update of this document will be done in conjunction with our WPAS report.

Where we are now:

Presently the Controls Department supports a variety of hardware architecture's including: Multibus I, Multibus II, VMEbus, VXIbus, and CAMAC. Our network technologies include Token Ring, Ethernet, ARCnet, GPIB and a very small amount of MIL-1553. This diversity places extraordinary requirements on us in terms of staffing.

We have a considerable investment in CAMAC that cannot be ignored. We will continue to support CAMAC for the foreseeable future. CAMAC is still a cost effective solution for many problems. Table I is a list of all of the presently supported CAMAC modules. Red modules will need some redesign due to obsolete parts before more modules can be constructed. Green modules will no longer be produced.

Tables II-V are lists of all the presently supported embedded systems and associated hardware.

More and more data collection is requested for study purposes as well as for operations of an increasingly complicated accelerator complex. The planned improvements to the accelerators at Fermilab will carry us into the next century. However, the majority of our data acquisition subsystems have their roots anchored in the technology of the 70's and early 80's. Many of our systems are already experiencing performance limitations in terms of processing and throughput capabilities.

Quite often we are asked on very short notice to interface to new systems or provide data acquisition and controls for new devices.

The hardware staff currently supports an installed equipment base of nearly 10,000 modules. We have a small number of people to maintain these systems. Some systems have only one expert for emergency call-in. With an average equipment age of 15+ years it should be no surprise to discover that maintenance activities now dominate our daily operations.

The funding level for our efforts has been shrinking rather than advancing. We are continually expected to do more with less.

Where we would like to be:

1. Upgrade-able Systems:

We would like to be in a position that will allow us to easily upgrade systems. We would like to be using standards that will ease the reuse of software and encourage the use of Object Oriented Software.

2. Data Throughput:

We want to be capable of delivering the amount of data required by studiers as well as normal operations in a timely, reliable manner.

3. System Maintenance:

We would like Controls people to spend less time maintaining equipment and diagnosing problems so more time is available for new designs and improvements.

4. Service to other Accelerator Departments:

The Controls Department would like to deliver systems that meet the requesters requirements and deadlines. We want to be able to accurately estimate whether we have the personnel to meet deadlines.

We want to be able to predict future demand for various modules and systems already supported by the department. We want to be able to respond quickly to requests for new systems.

How we will achieve our goals:

1. Upgrade-able Systems:

While developing new systems, we will work closely with the Microprocessor Group from the beginning of a project. In order to minimize the impact of software development licensing, etc., we will use the operating system(s) and processor boards supported by the Microprocessor Group. We will use commercial boards wherever practical.

We will institute and follow a review process for projects. The reviews shall emphasize modular hardware and software to facilitate upgrades. The attached review guidelines will be followed.

New systems will be either VMEbus, PLC or CAMAC depending on the scope of the project. No new Multibus II solutions will be built and in-house designs will be used only when standard solutions are not possible.

2. Data throughput:

We will identify the problem systems, work with users to find ways to reduce network traffic and upgrade systems as necessary. We will maintain a prioritized list of systems to be replaced as soon as funds are available, see attached list.

3. System Maintenance:

We would like to more effectively use our staff by dispatching technicians and operators to diagnose and solve problems first. Engineers will respond to problems that technicians have failed to solve. We want several people to be capable of diagnosing and repairing each of our systems.

To do this we will need to develop our staff. Each technician and staff member should have a clear understanding of the overall Control System and how data flows through the system. We will use the Monday morning coffee break to introduce different aspects of the controls system each week. These presentations will be summarized and added to the Controls Web site.

For large projects, we will design in teams so that more than one person is familiar with each system.

Each system will have a hardware manual which will include all the drawings, block diagrams, and hardware releases related to that system. An extra copy of these manuals will be available in the Linac Development Area bookcases.

All Controls Department spares will be in a central location within the responsible Engineering Group's area and clearly marked as to it's condition and the system in which it is to be used. For the convenience of the Operations group, one spare of each type of Camac module which is normally changed by operators during off hours will be kept in the cabinet located in the outer MCR.

The systems designers and reviewers will emphasize easy to understand systems with diagnostics ( leds, error logs, built-in tests, etc.).

4. Service to other Accelerator Departments:

We will institute a system for interfacing with other departments. This will include a form ( see appendix) for requesters to fill out information specifying their hardware requirements, software support requirements, a project deadline and budget. The request will be submitted to the Deputy Department Head who will assign appropriate personnel. The assigned personnel will ask for any additional input and then present a proposal for Controls Department Review. After the Departmental Review, a written proposal will be presented to the requester(s) who will have an opportunity to accept the proposal or explain why it doesn't meet the requirements. If minor changes need to be made, another Departmental Review would not be required.

The Deputy Department Head will poll the various Accelerator Division Departments regarding their plans for future installations. A current list of projects with assigned project leaders, review and completion dates, as well as budget information will be maintained by the Deputy Department Head and reviewed periodically by the Department Head and Group Leaders for planning purposes.

We will institute a database on the NT server that will allow us to monitor the inventory of various modules and equipment. This database will include the information from the other Departments regarding their future requirements, the present number of available hardware and the number of each in service.

How we will measure our progress:

1. Upgrade-able Systems:

Measuring our progress quantitatively on this goal will not be possible for several years. One way is to measure the personnel effort required to upgrade a particular system following our new guidelines and compare to the effort required for the next upgrade of that system.

2. Data Throughput:

Presently, we are asked for more and more data at faster and faster rates. If we are successful with this goal, our systems will be able to meet the specifications requirements which will now be automatically documented on the Engineering Request Form.

3. System Maintenance:

We will keep track of the amount of downtime charged to the Controls Department as well as the time spent by personnel in repairing equipment. Both of these should go down after some initial increase due to training and implementation of new systems.

4. Service to other Accelerator Departments:

If we provide better service to other departments, we will see an increase in the number of projects other departments ask us to do. Other departments will bring their work to us instead of hiring their own specialists for their department.

Controls Department Engineering Request Form

Requestor-			Today's Date-
Requestor's Dept-		Phone-
Budget Code-			Completion Date-
Budget allowance-		Priority-


Description of Request: (Include quantity  and locations )










Specifications: ( Please include voltage ranges, numbers of channels, resolution, speed  and noise requirements, etc.)

















For Controls Use:
ERF#			Implementor-
Review Date-		Completion Date-




TABLE  I


	MOD NO	DESCRIPTION				  		Maintainer	#

	052	QUAD UNIPOLAR DAC/PS CONTROLLER (12 BIT +P)		MASON		61
	053	QUAD BIPOLAR DAC/PS CONTROLLER (12 BIT)      		MASON		238
	054	HEX UNIPOLAR DAC (16 BIT)		     		MASON		31
	055*	VECTORED 16 BIT DIGITAL OUTPUT/DAC           		MASON		29
	057	STEPPING MOTOR CONTROLLER                    		FRANCK		75
	064*	OCTAL GATE GENERATOR			     		MASON		31
	066	BEAM/TIMING SYNC GENERATOR		     		MASON	
	068*	TCLK PROCESSOR FOR 070/071		     		MASON		5
	069*	MRRF TIMING PROCESSOR                        		MASON	
	070	CURVE TIME GENERATOR (1K x 24)		     		MASON		4
	071	CURVE VALUE GENERATOR (1K x 24)			     	MASON		17
	072	HEX EVENT RECORDER DATA BUFFER (1.5K x 16)   		MASON	
	073     BLOCK TRANSFER CONTROLLER				HENDRICKS
	080	PIO INTERFACE						MASON		194
	082	TANK FARM INTERFACE					MASON		2
	112	PARALLEL PRINTER INTERFACE                   		FRANCK		18
	114	SERIAL PRINTER INTERFACE		     		FRANCK		13
	117	SWIC CONTROLLER (119 WITHOUT DAC)            		FRANCK		11
	118	POWER SUPPLY CNTRLLR (16 BIT DAC, +5V STAT)  		FRANCK		60
	119	POWER SUPPLY CNTRLLR (16 BIT DAC, -24V STAT) 		FRANCK		218
	145*	MAIN RING VACUUM READBACK INTERFACE          		SEINO		35
	148     	MAIN RING RACK MONITOR                       	SEINO		0
	153*	QUAD BIPLR DAC/PS CNTRLR (12 BIT) - 2 STATE  		MASON
	160*	CORRECTION ELEMENT WAVEFORM GEN (12 BIT DAC) 		MCCLURE		301
	161	CORRECTION ELEMENT RAW PS CONTROLLER         		MCCLURE		28
	164*	WAVEFORM GEN/PS CNTRLR (16 BIT DAC, FAST UD) 		FRANCK		60
	165*	WAVEFORM GEN/PS CONTROLLER (16 BIT DAC)      		FRANCK		120
	166*	MDAT TRANSMITTER            		     		MASON		26
	169*	MDAT RECEIVER				     		MASON		95
	170	CIA CRATE/VACUUM CONTROLLER                  		LACKEY		60
	172*	TCLK TIME LINE GENERATOR                     		FRANCK		2
	175 	TCLK HARDWARE ENCODER			     		MCCLURE		31
	176	TCLK TRANSMITTER			     		MCCLURE		3
	177*	TCLK OCTAL TIMER			     		FRANCK		95
	178*	TCLK REPEATER/DECODER			     		McCLURE		109
	179*	PHASE REVERSAL GENERATOR		     		FRANCK		2
	180	MUXED DIGITAL I/O (12 C, 256 M)	             		MASON		124
	181	DIGITAL I/O (12 C, 16 M)		     		MASON		103
	182	DIGITAL OUTPUT (32 C - ACTIVE HIGH)	     		MASON		114

	* Denotes TCLK Input Provision.        no more will be built,    redesign before more can be built





TABLE  I  (cont)
             
	183	DIGITAL OUTPUT (32 C - ACTIVE LOW)           		MASON		2
	184	DIGITAL I/O (16 M, 16 C, 2 P)                		MASON		120
	185	DIGITAL INPUT (32 M, 2 P)                    		MASON		69
	186	MUXED DIGITAL I/O (12 PC, 256 M)	     		MASON		28
	187	MULTIPLEXED DIGITAL 0UTPUT (256 C, 16 M)     		MASON	
       	189    	MR INTENSITY SAMPLE                  			MASON
	190*	MADC CONTROLLER (12 or 14 BIT)	             		FRANCK		210
	191*	QUAD CHANNEL FAST DIGITIZER (12 BIT)         		FRANCK		25
	192*	QUAD CHANNEL FAST DIGITIZER (WIRE SCANNER)   		FRANCK		13
	193*	EIGHT CHANNEL TRANSIENT RECORDER/DIGITIZER   		SEINO		33
	200*	ABORT CONCENTRATOR			     		MASON		102
	201*	ABORT LINK GENERATOR			     		MASON		6
	220	COUNT TOTALIZER                              		FRANCK		12
       	265*    	WAVEFORM GEN/PS CONTROLLER (16 BIT DAC)      	FRANCK		22
	266*	TIME AT 150 GeV GENERATOR                    		MASON		2
	269	MAIN RING POWER SUPPLY LINK RECEIVER         		MASON		28
        270    	MR BPM FLASH EVENT TIMING PROCESSOR	         	MCCLURE
	276	BEAM SYNC CLOCK TRANSMITTER                  		MCCLURE		5
	278     	BEAM SYNC CLOCK REPEATER/DECODER             	McCLURE		10
	279*    	BEAM SYNC CLOCK INTERFACE/TIMER (2 CHANNEL)  	MASON		86
	280*	BSCLK TRIGGER PROCESSOR					MASON		2
	281*	BSCLK TRIGGER PROCESSOR					MASON		2
	282* 	BSCLK TRIGGER PROCESSOR                     		MASON		2
	283	BEAM SYNC 7.5 MHZ GAP DETECTOR               		MASON		2
	284	DIGITAL I/O (16 M, 16 PULSED C)              		MASON		55
	287*    TCLK INTERFACE/TIMER (2 CHANNEL)       			MASON		14
	288    	OCTAL PULSE DELAY              				MASON
	290	Updated 190						FRANCK		50
	333*	EIGHT CHANNEL 24 BIT BINARY SCALER           		MASON		8
	334*	SVX RAD SCALER (SHRT-MED-LONG INTERVAL)      		MASON	
       	335/336*SVX RADIATION DOSE MONITOR      	  		MASON
	365*   	 DIGITAL FUNCTION GENERATOR WITH 16 BIT DAC   		FRANCK		42
	372*	DIGITAL FUNCTION GENERATOR ( FAST 32 BITS)		MASON		2
	377	TCLK OCTAL TIMER - IMPROVED 177              		FRANCK		242	
	379	BEAM SYNC CLOCK OCTAL TIMER - IMPROVED 277   		FRANCK		21
	384    	BIWER BOX INTERFACE            				MASON		2
	453*	QUAD WAVEFORM GENERATOR/PS CONTROLLER      	  	FRANCK		80
	465*   	WAVEFORM GEN/PS CNTRLR - 16 BIT BP DAC       		FRANCK		245
	466*   	WAVEFORM GEN/PS CNTRLR - 16 BIT UP DAC       		FRANCK		8
	467*   	WAVEFORM GEN/PS CNTRLR - 16 BIT BP DIGITAL   		FRANCK		24
	468*   	WAVEFORM GEN/PS CNTRLR - 16 BIT UP DIGITAL   		FRANCK		31
	477*	TCLK QUAD TIMER - SET ON EVENT CAPABILITY    		FRANCK		2
	488*	GPIB CONTROLLER				     		SEINO		37
	489*	GPIB CONTROLLER	(WITH MORE MEMORY)	  	   	SEINO		35
	491*   	QUAD BUNCH INTENSITY DIGITIZER               		FRANCK		0
	500	LITTLE BIT OF EVERYTHING - TCLK	             		DUPUIS		2
	1553	MIL 1553B CONTROLLER			     		SEINO		11
	TSCC	TEVATRON SERIAL CRATE CONTROLLERS           		MASON		313
		Camac Crate Power Supplies and Fan Packs		MASON		297





TABLE II

Controls Department  Multibus I  Systems and Cards

 
System				Maintainer		Number (excluding spares)

BPM - MR, TEV 			Lackey		61
BPM- Pbar,8 Gev			Lackey		18
QPM (switchyard)		Lackey		3
Baker				McClure		1	

Cards		systems		Maintainer

M080		(all multibus I)	
68000uP	QXR,QPM				EE Support	
PRO		BPM			Marquardt		80	
8004		BPM			Marquardt		80
clock		BPM			Marquardt		80
TBT		BPM			Marquardt		80
FAB		BPM			Marquardt		15
TEX		BPM			Marquardt		80



TABLE III 


Controls Department  Multibus II  Systems and Cards

System				Maintainer		Number(excluding spares)

CAMAC front-end			Marquardt		8	
Frig				Marquardt		9


Cards		Systems		Maintainer		Number

386 sbx	FE,Frig			Marquardt		57 
leds+switches	FE,Frig		Franck			57
PCAT		FE,Frig		Marquardt		17
Token Ring	FE,Frig		Marquardt		17
Memory		FE,Frig		Marquardt		17
					








TABLE IV

Controls Department VMEbus Systems and Cards

System				Maintainer		Number (excluding spares)

BPM-400 Mev, Booster		Lackey			8
QPM- Low Beta			Lackey			2
UCD				Briegel			2
Rad Mon				Anderson		1
GFSDA				Briegel			1
IRM/VME				Shea			104
SRM				Shea			70
MI-Vacuum			Franck			18
SWIC				Franck			1
New QXR				Seino			1

Cards		Systems			Maintainer		Number

MVME133a	SRMs			Shea			63

Force 040	QPM, BPM (booster)	Lackey			8
		UCD			Briegel			2
		Consolidator		Lublinsky		1

MVME147

MVME162		ACNETbox		Briegel			2
		 MI-Vac			Franck	 		18
		IRM/VME			Shea			41	
		SWIC			Franck			1

Control		QPM			Lackey			2
Scaler		QPM			Lackey			6
GFC		QPM			Lackey			4
SSM		(all VME)		McClure			25
UCD		(most VME)		McClure			20
V177		Linac,			McClure			32

		

	
		



TABLE V


Other Controls Department  systems, modules and cards

System	Module			Maintainer	Number
Frig	Thermometry		Franck		31
Frig	FiFo			Franck		40
Frig	F2ADC			Seino		80  (+32 spare)
Frig	F2CPU			Seino		40  (+14 spare)
Frig	F2 Crate		Seino		40  (+12 spare)
Frig 	Actuator		Marquardt	650
Frig	Engine			Marquardt	160
Frig	Digital I/O		Marquardt	80


MADC	MADC I   Chassis	Seino		116 ( + 3 spare)
MADC	MADC II  Chassis	Seino		47    (+ 12 spare)
	
SEM				Zuchnik		9
STEG				Zuchnik		9
DRF tuning		 	Zuchnik		1
CIA crates			Zuchnik		45
CIA crate PS			Zuchnik		45
CIA crate driver cards		Zuchnik		45
Daughter Trigger Generators	Zuchnik		8 (+2 spares)

RF Link Repeaters		Mason		919
Fiber Optic Link Repeaters	Mason		290
RF MIUs  & P.S.			Mason		39
CCIUs & P.S.			Mason		4
CCIU expansion chassis		Mason		1
MADCs (DSE)			Mason		42
Digital Cross Connect Chassis	Mason		39
RF timing Units			Mason		3
TTL to 50 ohm Interfaces	Mason		4
BSTR Curve Generator Crate (NIM) Mason		2
BSTR Curve Generator Modules (NIM) Mason	10
E48/F11 Damper Controls 	Mason		1
Beam Switch Sum Boxes		Mason		2
Beam Switch Boxes at consoles	Mason		10
TCLK/MDAT  Fanout Chassis	Mason		34

Guidelines for Review of Controls Projects

A.  Which projects require a formal review?
		
	Projects that involve "considerable" hardware and/or software effort, time
	and/or money as determined at Group Leaders Meetings.

B.  Why do we need to have a formal review?

	The purpose of the review is to make sure that we don't waste time and
	money and that we are not surprised by some unknown requirements.
	Reviewers need to remember to be objective.  There are usually several
	ways of doing things.  If people have no freedom in designs, they are
	not designing.

C.  What exactly is a review?

	A review is a meeting with both systems people and controls people where
	constructive comments can be made.  It occurs before building a prototype
	but after a lot of informal discussions and meetings have already taken
	place.  If you know about the project and think you have important
	information, don't wait until the formal review to tell someone.  This is the
	last chance to make a significant change before a prototype is built.

	The project leader's presentation at the review should follow this general
	outline:

		1.  Why is this project needed?  What are the requirements?

		2.  What were the alternatives considered?

		3.  What is the solution proposed and why.

		4.  Cost in time and money needed for the project.

		5.  Schedule.

	The reviewers should try to limit their criticism to the following:

		1.  Does the design meet the requirements?

		2.  Do we have the resources to meet the deadlines?

		3.  Is there something that may have been overlooked that would impact
		    this design?

		4.  Does the design impact other operational systems?  Are there safety
		    issues?

		5.  Is the implementation consistent with our Strategic Plan?

C.  Who reviews?

	Controls Group Leaders,  Systems representatives, Operations  representatives
	and occasionally Division representatives.   Review will be set up by the
	Controls Department Head.	


Systems to be Replaced in Priority Order

High Level RF (Main Ring, Tev) Replace C190s that need more plot channels with C290s C160 replacement Timeline Generator GPIB ( Camac 488, 489) Vacuum (Camac 170, CIA crate interface and power supply) MDAT generator Main Injector BPMs Switchyard QPMs Tevatron QPMs Tevatron BPMs MTOS sytems upgraded to VxWorks ( Booster BPMs, Low Beta QPMs) Replace Camac Power Supplies Stochastic Cooling