Proposed Distributed A-D System

Mike Shea
February 23, 2000


From the discussions about new analog digitizers, it seems that there are two main classes of analog signals: slow and fast. The slow signals are those that come from dc, sample and hold, or slowly varying signal sources- slow enough that high input impedance digitizers may be used without worrying about cable reflections. Fast signals typically come from sources that can drive 50 ohm cable and need termination to avoid distortion from termination mismatch. For this discussion, the maximum sampling rate of the slow and fast signals is taked to be 10 kHz and 20 MHz, respectively.

Console use of Slow Signals:

Slow signals will be used by console programs like the Parameter Page to display slowly changing samples of the signal or the Fast Time Plots that plot data continuously. The frequency of FTP data would be one to a few kHz continuous. Slow data could also be displayed as snapshot plots up to the maximum sample rate of 10 kHz. These services would be available for all channels simultaneously - the data are acquired and stored continuously, and selected data is returned to the consoles as needed.

Console use of Fast Signals:

Fast signals would be digitized at rates from slightly beyond the capability of the slow digitizer system up to digitize rates of ten or tens of MHz. The data would be presented in the snapshot mode. This type of data acquisition can accommodate signals like Linac beam, Booster injection and extraction signals, horn current profiles, etc. Acquisition is armed and triggered by any of several modes, including TClk event plus delay and External trigger. External digitize rate would also be supported to synchronize with external events, such as beam revolution frequency.


Since there are two very different signal types, the hardware can be tailored to the requirements of each. The slow signals could be packaged with 64 input channels and can be multiplexed. The fast signals can be packaged with a digitizer for each of 8 or 16 channels per module. The high speed data can be stored temporarily in FIFO memory and then transferred to RAM.

The suggestion that these digitizers be packaged in separate chassis solves problems associated with cabling all the analog signals to a VMEbus crate. By using a stand-alone chassis, that chassis may be taken offline without impacting other functions in a central VMEbus crate.

Consider an architecture where a single VMEbus crate acquires data from several remote digitizer chassis. If the connection is made using a simple but fast serial link, then from the processor end, the digitizer system can act as though it were local. Data can be directed to memory location addresses that map to registers in the remote hardware. A-D data transmitted from the remote hardware would be stored in local memory by the Altera chip.

Because single board computers are used that have either PMC or IP sockets, it would be good to implement the receiver on both mezzanine formats.

Proposed Design, slow digitizer

The proposed design for the slow digitizer:

If a single digitizer is used, the maximum sample rate for each of the 64 channels is about 4 kHz. To increase this rate to 10 kHz, four digitizers, each digitizing 16 analog channels will be used. Output from the four digitizers would be interleaved in the returning data stream and steered to the appropriate memory location pointed to by the channel number. Then blocks of 64 channels could be digitized and sent to the host computer every 100 microseconds.

The receiver and data storage.

Serial data returned by the digitizer box will be received and stored in memory on IP or PMC modules by an Altera chip operating without processor intervention. A similar serial link would carry commands and settings to the digitizer box. The amount of memory on the receiver board should be sufficient to contain data for about 1 second before overwriting old data. For 10kHz sampling, this requires 10,000 x 64 words or 1.28 MBytes of memory. The main memory would be dual ported so it can be written by an Altera FPGA and also accessed by the host computer. It is important that the digitizer data be stored in the proper place in memory. To do this, each incoming reading should be accompanied by its channel number, which will be used as part of the address for storing the data. Blocks of 64 channels of A-D data are stored in a circular buffer one second long, and data is overwritten as new data arrives. The host processor can learn where data is being stored by reading the memory pointer used by the Altera FPGA to store the data. In order to timestamp data being returned to consoles, the host processor will be interrupted when the last channel of a 64 channel block is written to memory. However, this would cause interrupts to occur at a 10kHz rate. A slower interrupt rate is possible if the Altera chip generated an interrupt after storing, say, 16 sets of 64 readings.

The Altera chip contains other registers that hold miscellaneous data returned from the digitizer box. The box could be expanded to include several bytes of digital I/O and analog output data.

Data representation on the serial line.

Each remote module would have both a transmit and a receive serial link. For uniformity and for future use, each transmission could be 4 bytes long, two bytes of data and two bytes for other information; the type of data being transmitted, the channel number of the data, the address of the target register, etc. The logic for receiving data would be the same for both the mezzanine board and the digitizer box– serial data received and assembled into a parallel byte by the LVDS chip; four bytes would be arranged as 2 16-bit address/control and data words. All data stored in memory should be left justified two’s-complement values.

Reading and setting miscellaneous registers.

The fast serial link coupled with the Altera chip makes the digitizer system appear to be memory mapped- especially for settings. For reading remote registers, there would be a latency involved and it would be difficult for the host to know when register readings had been received. This could be avoided if the remote digitizer box sent back the values in all its registers repetitively at a rate of 15 Hz or higher. The number of these miscellaneous registers is small and they can be implemented as RAM modules in the Altera chip.

Optional features

Given the logic to read and write 16-bit registers, it would be easy to include the some analog control and digital I/O similar to that of the various Rack Monitors. Those devices include 8 bytes of digital I/O, and eight D-As.

Physical chassis

A 1U chassis should be enough height to accommodate the remote digitizer and its power supply. The connector arrangement of four 37-pin connectors, each carrying 16 analog channels, has worked well for the Rack Monitor installations. This arrangement provides modularity to allow some users to connect via 37-conductor ribbon cables, while other users may need breakout panels with BNC or Twinax connectors. The attached figure shows a possible back panel arrangement for the Slow Serial Digitizer with and without the additional Quikr Digitizers. If Quikr Digitizer channels are included, a 2U chassis would be required. The figure shows the digital and analog output data connectors. For the sake of compatibility, it would be useful to retain the pinout assignments used on rack monitors.

Fast Data Acquisition

Fast data is acquired as snapshot data. That is, the digitizers are triggered to acquire a one shot sequence of data that will be transmitted to the receiver card and used by the console for snapshot plots. The sequence is armed by the host computer and triggered by either an external trigger or by an event-plus-delay trigger derived from a TClk processor. The Altera chip in the remote unit would provide the TClk processing and the delay necessary to trigger the digitizer.

As an example, the snapshot digitizer unit could be 8 or 16 channels operating at digitize frequencies of 20 MHz or lower. Such digitizer chips with 12 bit resolution are available from Burr Brown and others. Each channel has a separate digitizer chip and digitized data would flow into separate FIFO memories. The Altera chip would transmit data to the host computer via the LVDS serial link. The data type and channel number would allow the receiver to direct the fast A-D data to the appropriate memory locations. For a FIFO depth of 16k words for 8 channels, the total amount of data to transmit at 4 bytes per word is 256k Bytes. It may be possible to configure the slow digitizer box to accept the fast digitizer as an optional plug in daughterboard. If that were done, then a single link and receiver board would take care of both slow and fast digitizer data.


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